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Commit 77b339bc authored by Yan, Zheng's avatar Yan, Zheng Committed by Ingo Molnar
Browse files

perf/x86/intel/uncore: Enable EV_SEL_EXT bit for PCU 



This patch adds support for the SNB-EP PCU uncore PMU extra_sel_bit
(bit 21) which is missing from the documentation in Table-2.75 of
Intel Xeon Processor E5-2600 Product Family Uncore Performance
Monitoring Guide. It is referred to later in Table-2.81. Without
this selection bit explicitly enabled by the kernel, some events
such as COREx_TRANSITION_CYCLES do not count correctly.

Signed-off-by: default avatarYan, Zheng <zheng.z.yan@intel.com>
Reviewed-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1376375382-21350-4-git-send-email-zheng.z.yan@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent fd1ec259

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -301,7 +301,7 @@ static struct attribute *snbep_uncore_cbox_formats_attr[] = { 
};



static struct attribute *snbep_uncore_pcu_formats_attr[] = {

	&format_attr_event.attr,

	&format_attr_event_ext.attr,

	&format_attr_occ_sel.attr,

	&format_attr_edge.attr,

	&format_attr_inv.attr,

arch/x86/kernel/cpu/perf_event_intel_uncore.h

+1 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ 
				(SNBEP_PMON_CTL_EV_SEL_MASK | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \

				 SNBEP_PMON_CTL_EDGE_DET | \

				 SNBEP_PMON_CTL_EV_SEL_EXT | \

				 SNBEP_PMON_CTL_INVERT | \

				 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \