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Commit 77961eb9 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915: power domains: add vlv power wells 



Based on an early draft from Jesse.

Add support for powering on/off the dynamic power wells on VLV by
registering its display and dpio dynamic power wells with the power
domain framework.

For now power on all PHY TX lanes regardless of the actual lane
configuration. Later this can be optimized when the PHY side setup
enables only the required lanes. Atm, it enables all lanes in all
cases.

v2:
- undef function local COND macro after its last use (Ville)
- Take dev_priv->irq_lock around the whole sequence of
  intel_set_cpu_fifo_underrun_reporting_nolock() and
  valleyview_disable_display_irqs(). They are short and releasing
  the lock in between only makes proving correctness more difficult.
- sanitize local var names in vlv_power_well_enabled()
v3:
- rebase on latest -nightly

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Resolve conflict due to my changes in the previous patch.
Also throw in an assert_spin_locked for safety. And finally appease
checkpatch.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f88d42f1

drivers/gpu/drm/i915/i915_dma.c

+0 −1
Original line number Diff line number Diff line
@@ -1672,7 +1672,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		goto out_mtrrfree;

	}



	dev_priv->display_irqs_enabled = true;

	intel_irq_init(dev);

	intel_uncore_sanitize(dev);

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1062,7 +1062,7 @@ struct i915_power_well { 
	/* power well enable/disable usage count */

	int count;

	unsigned long domains;

	void *data;

	unsigned long data;

	const struct i915_power_well_ops *ops;

};

drivers/gpu/drm/i915/i915_irq.c

+2 −0
Original line number Diff line number Diff line
@@ -395,6 +395,8 @@ bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	bool ret;



	assert_spin_locked(&dev_priv->irq_lock);



	ret = !intel_crtc->cpu_fifo_underrun_disabled;



	if (enable == ret)

drivers/gpu/drm/i915/intel_display.c

+1 −0
Original line number Diff line number Diff line
@@ -4229,6 +4229,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev) 


	if (req_cdclk != cur_cdclk)

		valleyview_set_cdclk(dev, req_cdclk);

	modeset_update_crtc_power_domains(dev);

}



static void valleyview_crtc_enable(struct drm_crtc *crtc)

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -609,6 +609,8 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 
/* i915_irq.c */

bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,

					   enum pipe pipe, bool enable);

bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,

					     enum pipe pipe, bool enable);

bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,

					   enum transcoder pch_transcoder,

					   bool enable);