Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7762ebb9 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
Browse files

drm/i915/guc: Release GuC interrupts in i915_guc_submission_disable 



Like capture of GuC interrupts while enabling GuC submission, release
them while disabling GuC submission.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489199821-6707-1-git-send-email-sagar.a.kamble@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 7c0a16ad

drivers/gpu/drm/i915/i915_guc_submission.c

+23 −0
Original line number Diff line number Diff line
@@ -995,10 +995,33 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) 
	return 0;

}



static void guc_interrupts_release(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	int irqs;



	/*

	 * tell all command streamers NOT to forward interrupts or vblank

	 * to GuC.

	 */

	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);

	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);

	for_each_engine(engine, dev_priv, id)

		I915_WRITE(RING_MODE_GEN7(engine), irqs);



	/* route all GT interrupts to the host */

	I915_WRITE(GUC_BCS_RCS_IER, 0);

	I915_WRITE(GUC_VCS2_VCS1_IER, 0);

	I915_WRITE(GUC_WD_VECS_IER, 0);

}



void i915_guc_submission_disable(struct drm_i915_private *dev_priv)

{

	struct intel_guc *guc = &dev_priv->guc;



	guc_interrupts_release(dev_priv);



	if (!guc->execbuf_client)

		return;

drivers/gpu/drm/i915/intel_guc_loader.c

+0 −21
Original line number Diff line number Diff line
@@ -91,24 +91,6 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) 
	}

};



static void guc_interrupts_release(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	int irqs;



	/* tell all command streamers NOT to forward interrupts or vblank to GuC */

	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);

	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);

	for_each_engine(engine, dev_priv, id)

		I915_WRITE(RING_MODE_GEN7(engine), irqs);



	/* route all GT interrupts to the host */

	I915_WRITE(GUC_BCS_RCS_IER, 0);

	I915_WRITE(GUC_VCS2_VCS1_IER, 0);

	I915_WRITE(GUC_WD_VECS_IER, 0);

}



static u32 get_gttype(struct drm_i915_private *dev_priv)

{

	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -429,7 +411,6 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) 
		goto fail;

	}



	guc_interrupts_release(dev_priv);

	gen9_reset_guc_interrupts(dev_priv);



	/* We need to notify the guc whenever we change the GGTT */
@@ -496,7 +477,6 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) 
	if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)

		guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;



	guc_interrupts_release(dev_priv);

	i915_guc_submission_disable(dev_priv);

	i915_guc_submission_fini(dev_priv);

	i915_ggtt_disable_guc(dev_priv);
@@ -746,7 +726,6 @@ void intel_guc_fini(struct drm_i915_private *dev_priv) 
	struct drm_i915_gem_object *obj;



	mutex_lock(&dev_priv->drm.struct_mutex);

	guc_interrupts_release(dev_priv);

	i915_guc_submission_disable(dev_priv);

	i915_guc_submission_fini(dev_priv);

	mutex_unlock(&dev_priv->drm.struct_mutex);