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Commit 77451997 authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle
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MIPS: pm-cps: Support CM3 changes to Coherence Enable Register 



MIPS CM3 changed the management of coherence. Instead of a coherence
control register with a bitmask of coherent domains, CM3 simply has a
coherence enable register with a single bit to enable coherence of the
local core. Support this by clearing and setting this single bit to
disable / enable coherence.

Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Tony Wu <tung7970@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nikolay Martynov <mar.kolya@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14226/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 929d4f51

arch/mips/include/asm/mips-cm.h

+1 −0
Original line number Diff line number Diff line
@@ -359,6 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) 
/* GCR_Cx_COHERENCE register fields */

#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF	0

#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK	(_ULCAST_(0xff) << 0)

#define CM3_GCR_Cx_COHERENCE_COHEN_MSK		(_ULCAST_(0x1) << 0)



/* GCR_Cx_CONFIG register fields */

#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF		10

arch/mips/kernel/pm-cps.c

+18 −13
Original line number Diff line number Diff line
@@ -480,10 +480,11 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) 
	uasm_i_sync(&p, STYPE_SYNC);

	uasm_i_ehb(&p);



	if (mips_cm_revision() < CM_REV_CM3) {

		/*

	 * Disable all but self interventions. The load from COHCTL is defined

	 * by the interAptiv & proAptiv SUMs as ensuring that the operation

	 * resulting from the preceding store is complete.

		* Disable all but self interventions. The load from COHCTL is

		* defined by the interAptiv & proAptiv SUMs as ensuring that the

		*  operation resulting from the preceding store is complete.

		*/

		uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);

		uasm_i_sw(&p, t0, 0, r_pcohctl);
@@ -492,6 +493,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) 
		/* Barrier to ensure write to coherence control is complete */

		uasm_i_sync(&p, STYPE_SYNC);

		uasm_i_ehb(&p);

	}



	/* Disable coherence */

	uasm_i_sw(&p, zero, 0, r_pcohctl);
@@ -566,7 +568,10 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) 
	 * will run this. The first will actually re-enable coherence & the

	 * rest will just be performing a rather unusual nop.

	 */

	uasm_i_addiu(&p, t0, zero, CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK);

	uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3

				? CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK

				: CM3_GCR_Cx_COHERENCE_COHEN_MSK);



	uasm_i_sw(&p, t0, 0, r_pcohctl);

	uasm_i_lw(&p, t0, 0, r_pcohctl);