Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 75e03512 authored by Vivek Natarajan's avatar Vivek Natarajan Committed by John W. Linville
Browse files

ath9k_hw: Fix PLL initialization for AR9485. 



Increase the delay to make sure the initialization of pll
passes.

Signed-off-by: default avatarVivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 7ea1362c

drivers/net/wireless/ath/ath9k/hw.c

+2 −2
Original line number Diff line number Diff line
@@ -701,7 +701,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, 
			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);



		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);

		udelay(100);

		udelay(1000);



		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
@@ -713,7 +713,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, 
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,

			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);

		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);

		udelay(110);

		udelay(1000);

	}



	pll = ath9k_hw_compute_pll_control(ah, chan);