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Commit 74f55d34 authored by Feng Kan's avatar Feng Kan Committed by Will Deacon
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iommu/arm-smmu: Enable bypass transaction caching for ARM SMMU 500 



The ARM SMMU identity mapping performance was poor compared with the
DMA mode. It was found that enable caching would restore the performance
back to normal. The S2CRB_TLBEN bit in the ACR register would allow for
caching of the stream to context register bypass transaction information.

Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarFeng Kan <fkan@apm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 704c0382

drivers/iommu/arm-smmu.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -59,6 +59,7 @@ 
#define ARM_MMU500_ACTLR_CPRE		(1 << 1)

#define ARM_MMU500_ACTLR_CPRE		(1 << 1)





#define ARM_MMU500_ACR_CACHE_LOCK	(1 << 26)

#define ARM_MMU500_ACR_CACHE_LOCK	(1 << 26)

#define ARM_MMU500_ACR_S2CRB_TLBEN	(1 << 10)

#define ARM_MMU500_ACR_SMTNMB_TLBEN	(1 << 8)

#define ARM_MMU500_ACR_SMTNMB_TLBEN	(1 << 8)





#define TLB_LOOP_TIMEOUT		1000000	/* 1s! */

#define TLB_LOOP_TIMEOUT		1000000	/* 1s! */
@@ -1598,7 +1599,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 
		 * Allow unmatched Stream IDs to allocate bypass

		 * Allow unmatched Stream IDs to allocate bypass

		 * TLB entries for reduced latency.

		 * TLB entries for reduced latency.

		 */

		 */

		reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;

		reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;

		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);

		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);

	}

	}