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Commit 745c061f authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: limit interrupts supported by ColdFire intc-simr driver 



The intc-simr interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 6d0f33fa

arch/m68knommu/platform/coldfire/intc-simr.c

+24 −23
Original line number Original line Diff line number Diff line
@@ -20,40 +20,40 @@ 
#include <asm/mcfsim.h>

#include <asm/mcfsim.h>

#include <asm/traps.h>

#include <asm/traps.h>





/*

 *	There maybe one or two interrupt control units, each has 64

 *	interrupts. If there is no second unit then MCFINTC1_* defines

 *	will be 0 (and code for them optimized away).

 */



static void intc_irq_mask(struct irq_data *d)

static void intc_irq_mask(struct irq_data *d)

{

{

	unsigned int irq = d->irq;

	unsigned int irq = d->irq - MCFINT_VECBASE;





	if (irq >= MCFINT_VECBASE) {

	if (MCFINTC1_SIMR && (irq > 64))

		if (irq < MCFINT_VECBASE + 64)

		__raw_writeb(irq - 64, MCFINTC1_SIMR);

			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);

	else

		else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)

		__raw_writeb(irq, MCFINTC0_SIMR);

			__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);

	}

}

}





static void intc_irq_unmask(struct irq_data *d)

static void intc_irq_unmask(struct irq_data *d)

{

{

	unsigned int irq = d->irq;

	unsigned int irq = d->irq - MCFINT_VECBASE;





	if (irq >= MCFINT_VECBASE) {

	if (MCFINTC1_CIMR && (irq > 64))

		if (irq < MCFINT_VECBASE + 64)

		__raw_writeb(irq - 64, MCFINTC1_CIMR);

			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);

	else

		else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)

		__raw_writeb(irq, MCFINTC0_CIMR);

			__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);

	}

}

}





static int intc_irq_set_type(struct irq_data *d, unsigned int type)

static int intc_irq_set_type(struct irq_data *d, unsigned int type)

{

{

	unsigned int irq = d->irq;

	unsigned int irq = d->irq - MCFINT_VECBASE;





	if (irq >= MCFINT_VECBASE) {

	if (MCFINTC1_ICR0 && (irq > 64))

		if (irq < MCFINT_VECBASE + 64)

		__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);

			__raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);

	else

		else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)

		__raw_writeb(5, MCFINTC0_ICR0 + irq);

			__raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);

	}

	return 0;

	return 0;

}

}
@@ -66,7 +66,7 @@ static struct irq_chip intc_irq_chip = { 




void __init init_IRQ(void)

void __init init_IRQ(void)

{

{

	int irq;

	int irq, eirq;





	init_vectors();

	init_vectors();
@@ -75,7 +75,8 @@ void __init init_IRQ(void) 
	if (MCFINTC1_SIMR)

	if (MCFINTC1_SIMR)

		__raw_writeb(0xff, MCFINTC1_SIMR);

		__raw_writeb(0xff, MCFINTC1_SIMR);





	for (irq = 0; (irq < NR_IRQS); irq++) {

	eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);

	for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {

		set_irq_chip(irq, &intc_irq_chip);

		set_irq_chip(irq, &intc_irq_chip);

		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);

		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);

		set_irq_handler(irq, handle_level_irq);

		set_irq_handler(irq, handle_level_irq);