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Commit 740c606e authored by John Crispin's avatar John Crispin
Browse files

MIPS: lantiq: adds static clock for PP32 



The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/
parent 3d18c17e

arch/mips/include/asm/mach-lantiq/lantiq.h

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *clk); 
extern struct clk *clk_get_cpu(void);

extern struct clk *clk_get_fpi(void);

extern struct clk *clk_get_io(void);

extern struct clk *clk_get_ppe(void);



/* find out what bootsource we have */

extern unsigned char ltq_boot_select(void);

arch/mips/lantiq/clk.c

+10 −2
Original line number Diff line number Diff line
@@ -26,13 +26,15 @@ 
#include "prom.h"



/* lantiq socs have 3 static clocks */

static struct clk cpu_clk_generic[3];

static struct clk cpu_clk_generic[4];



void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)

void clkdev_add_static(unsigned long cpu, unsigned long fpi,

			unsigned long io, unsigned long ppe)

{

	cpu_clk_generic[0].rate = cpu;

	cpu_clk_generic[1].rate = fpi;

	cpu_clk_generic[2].rate = io;

	cpu_clk_generic[3].rate = ppe;

}



struct clk *clk_get_cpu(void)
@@ -51,6 +53,12 @@ struct clk *clk_get_io(void) 
	return &cpu_clk_generic[2];

}



struct clk *clk_get_ppe(void)

{

	return &cpu_clk_generic[3];

}

EXPORT_SYMBOL_GPL(clk_get_ppe);



static inline int clk_good(struct clk *clk)

{

	return clk && !IS_ERR(clk);

arch/mips/lantiq/clk.h

+6 −1
Original line number Diff line number Diff line
@@ -27,12 +27,15 @@ 
#define CLOCK_167M	166666667

#define CLOCK_196_608M	196608000

#define CLOCK_200M	200000000

#define CLOCK_222M	222000000

#define CLOCK_240M	240000000

#define CLOCK_250M	250000000

#define CLOCK_266M	266666666

#define CLOCK_300M	300000000

#define CLOCK_333M	333333333

#define CLOCK_393M	393215332

#define CLOCK_400M	400000000

#define CLOCK_450M	450000000

#define CLOCK_500M	500000000

#define CLOCK_600M	600000000
@@ -64,15 +67,17 @@ struct clk { 
};



extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,

				unsigned long io);

				unsigned long io, unsigned long ppe);



extern unsigned long ltq_danube_cpu_hz(void);

extern unsigned long ltq_danube_fpi_hz(void);

extern unsigned long ltq_danube_pp32_hz(void);



extern unsigned long ltq_ar9_cpu_hz(void);

extern unsigned long ltq_ar9_fpi_hz(void);



extern unsigned long ltq_vr9_cpu_hz(void);

extern unsigned long ltq_vr9_fpi_hz(void);

extern unsigned long ltq_vr9_pp32_hz(void);



#endif

arch/mips/lantiq/falcon/sysctrl.c

+2 −2
Original line number Diff line number Diff line
@@ -241,9 +241,9 @@ void __init ltq_soc_init(void) 


	/* get our 3 static rates for cpu, fpi and io clocks */

	if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)

		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);

		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);

	else

		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);

		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);



	/* add our clock domains */

	clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);

arch/mips/lantiq/xway/clk.c

+43 −0
Original line number Diff line number Diff line
@@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void) 
	}

}



unsigned long ltq_danube_pp32_hz(void)

{

	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;

	unsigned long clk;



	switch (clksys) {

	case 1:

		clk = CLOCK_240M;

		break;

	case 2:

		clk = CLOCK_222M;

		break;

	case 3:

		clk = CLOCK_133M;

		break;

	default:

		clk = CLOCK_266M;

		break;

	}



	return clk;

}



unsigned long ltq_ar9_sys_hz(void)

{

	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
@@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void) 


	return clk;

}



unsigned long ltq_vr9_pp32_hz(void)

{

	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;

	unsigned long clk;



	switch (clksys) {

	case 1:

		clk = CLOCK_450M;

		break;

	case 2:

		clk = CLOCK_300M;

		break;

	default:

		clk = CLOCK_500M;

		break;

	}



	return clk;

}