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Commit 7352fb5a authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
Browse files

drm/msm: Pass interrupt status to a5xx_rbbm_err_irq() 



The interrupt status was being cleared before processing the handlers.
a5xx_rbbm_err_irq() was checking the interrupt status again, which would
likely turn out bad because the interrupt status would be 0 (or at least
different). Pass the original status to the function instead.

Also, skip clearing RBBM_AHB_ERROR from the interrupt status. The interrupt
will keep firing until the error source is cleared.  Skip the clear to
avoid a storm until the error is cleared in a5xx_rbbm_err_irq().

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 36849cc3

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+13 −5
Original line number Diff line number Diff line
@@ -638,10 +638,8 @@ static void a5xx_cp_err_irq(struct msm_gpu *gpu) 
	}

}



static void a5xx_rbbm_err_irq(struct msm_gpu *gpu)

static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)

{

	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);



	if (status & A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR) {

		u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);
@@ -653,6 +651,10 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu) 


		/* Clear the error */

		gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4));



		/* Clear the interrupt */

		gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,

			A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);

	}



	if (status & A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT)
@@ -704,10 +706,16 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) 
{

	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);



	gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, status);

	/*

	 * Clear all the interrupts except RBBM_AHB_ERROR - if we clear it

	 * before the source is cleared the interrupt will storm.

	 */

	gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,

		status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);



	/* Pass status to a5xx_rbbm_err_irq because we've already cleared it */

	if (status & RBBM_ERROR_MASK)

		a5xx_rbbm_err_irq(gpu);

		a5xx_rbbm_err_irq(gpu, status);



	if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR)

		a5xx_cp_err_irq(gpu);