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Commit 71fbafcc authored by Austin Christ's avatar Austin Christ Committed by Wolfram Sang
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i2c: qup: Correct duty cycle for FM and FM+ 



The I2C spec UM10204 Rev. 6 specifies the following timings.

           Standard      Fast Mode     Fast Mode Plus
SCL low    4.7us         1.3us         0.5us
SCL high   4.0us         0.6us         0.26us

This results in a 33%/66% duty cycle as opposed to the 50%/50% duty cycle
used for Standard-mode.

Add High Time Divider settings to correct duty cycle for FM(400kHz) and
FM+(1MHz).

Signed-off-by: default avatarAustin Christ <austinwc@codeaurora.org>
Reviewed-by: default avatarSricharan R <sricharan@codeaurora.org>
Reviewed-by: default avatarAndy Gross <andy.gross@linaro.org>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 109b8c42

drivers/i2c/busses/i2c-qup.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -1855,9 +1855,15 @@ static int qup_i2c_probe(struct platform_device *pdev) 
	size = QUP_INPUT_FIFO_SIZE(io_mode);

	size = QUP_INPUT_FIFO_SIZE(io_mode);

	qup->in_fifo_sz = qup->in_blk_sz * (2 << size);

	qup->in_fifo_sz = qup->in_blk_sz * (2 << size);





	fs_div = ((src_clk_freq / clk_freq) / 2) - 3;

	hs_div = 3;

	hs_div = 3;

	if (clk_freq <= I2C_STANDARD_FREQ) {

		fs_div = ((src_clk_freq / clk_freq) / 2) - 3;

		qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);

		qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);

	} else {

		/* 33%/66% duty cycle */

		fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;

		qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);

	}





	/*

	/*

	 * Time it takes for a byte to be clocked out on the bus.

	 * Time it takes for a byte to be clocked out on the bus.