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Commit 70c8de0c authored by Kalle Valo's avatar Kalle Valo
Browse files
ath.git patches for 4.16. Major changes:

ath9k

* add MSI support (not enabled by default yet)
parents a64e7a79 a3e712b7
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+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ struct ath10k_ce_ops {
			      dma_addr_t buffer, u32 nbytes,
			      u32 transfer_id, u32 flags);
};

static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
{
	return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
+7 −7
Original line number Diff line number Diff line
@@ -1276,7 +1276,10 @@ static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
		len -= sizeof(*hdr);
		data = hdr->data;

		if (len < ALIGN(ie_len, 4)) {
		/* jump over the padding */
		ie_len = ALIGN(ie_len, 4);

		if (len < ie_len) {
			ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
				   ie_id, ie_len, len);
			ret = -EINVAL;
@@ -1315,9 +1318,6 @@ static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
			goto out;
		}

		/* jump over the padding */
		ie_len = ALIGN(ie_len, 4);

		len -= ie_len;
		data += ie_len;
	}
@@ -1448,6 +1448,9 @@ int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
		len -= sizeof(*hdr);
		data += sizeof(*hdr);

		/* jump over the padding */
		ie_len = ALIGN(ie_len, 4);

		if (len < ie_len) {
			ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
				   ie_id, len, ie_len);
@@ -1553,9 +1556,6 @@ int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
			break;
		}

		/* jump over the padding */
		ie_len = ALIGN(ie_len, 4);

		len -= ie_len;
		data += ie_len;
	}
+1 −0
Original line number Diff line number Diff line
@@ -1856,6 +1856,7 @@ struct ath10k_htt_rx_ops {
	void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt);
	void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);
};

#define RX_HTT_HDR_STATUS_LEN 64

/* This structure layout is programmed via rx ring setup
+1 −4
Original line number Diff line number Diff line
@@ -1478,13 +1478,10 @@ static int ath10k_pci_dump_memory_section(struct ath10k *ar,
	if (!mem_region || !buf)
		return 0;

	if (mem_region->section_table.size < 0)
		return 0;

	cur_section = &mem_region->section_table.sections[0];

	if (mem_region->start > cur_section->start) {
		ath10k_warn(ar, "incorrect memdump region 0x%x with section start addrress 0x%x.\n",
		ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
			    mem_region->start, cur_section->start);
		return 0;
	}
+26 −7
Original line number Diff line number Diff line
@@ -922,6 +922,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
	u32 msi_cfg = 0;

	if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
	    AR_SREV_9561(ah))
@@ -929,22 +930,30 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,

	if (AR_SREV_9300_20_OR_LATER(ah)) {
		imr_reg |= AR_IMR_RXOK_HP;
		if (ah->config.rx_intr_mitigation)
		if (ah->config.rx_intr_mitigation) {
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
		} else {
			imr_reg |= AR_IMR_RXOK_LP;

			msi_cfg |= AR_INTCFG_MSI_RXOK;
		}
	} else {
		if (ah->config.rx_intr_mitigation)
		if (ah->config.rx_intr_mitigation) {
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
		} else {
			imr_reg |= AR_IMR_RXOK;
			msi_cfg |= AR_INTCFG_MSI_RXOK;
		}
	}

	if (ah->config.tx_intr_mitigation)
	if (ah->config.tx_intr_mitigation) {
		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
	else
		msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR;
	} else {
		imr_reg |= AR_IMR_TXOK;
		msi_cfg |= AR_INTCFG_MSI_TXOK;
	}

	ENABLE_REGWRITE_BUFFER(ah);

@@ -952,6 +961,16 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);

	if (ah->msi_enabled) {
		ah->msi_reg = REG_READ(ah, AR_PCIE_MSI);
		ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
		ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
		REG_WRITE(ah, AR_INTCFG, msi_cfg);
		ath_dbg(ath9k_hw_common(ah), ANY,
			"value of AR_INTCFG=0x%X, msi_cfg=0x%X\n",
			REG_READ(ah, AR_INTCFG), msi_cfg);
	}

	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
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