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Commit 6fe27464 authored by Daode Huang's avatar Daode Huang Committed by David S. Miller
Browse files

net: hns: bug fix about TSO on|off when there is traffic 



When enable/disable tso, the driver tries to access the hardware register,
but this operation will cause the port unavalible when there is traffic.
This patch tries to enable TSO when initialize, then control tso through
TSE bit in transmit descriptor.

Signed-off-by: default avatarDaode Huang <huangdaode@hisilicon.com>
Signed-off-by: default avatarYisen Zhuang <Yisen.Zhuang@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f28f34cd

drivers/net/ethernet/hisilicon/hns/hns_enet.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -1441,7 +1441,6 @@ static int hns_nic_set_features(struct net_device *netdev, 
				netdev_features_t features)

				netdev_features_t features)

{

{

	struct hns_nic_priv *priv = netdev_priv(netdev);

	struct hns_nic_priv *priv = netdev_priv(netdev);

	struct hnae_handle *h = priv->ae_handle;





	switch (priv->enet_ver) {

	switch (priv->enet_ver) {

	case AE_VERSION_1:

	case AE_VERSION_1:
@@ -1454,11 +1453,9 @@ static int hns_nic_set_features(struct net_device *netdev, 
			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tso;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tso;

			/* The chip only support 7*4096 */

			/* The chip only support 7*4096 */

			netif_set_gso_max_size(netdev, 7 * 4096);

			netif_set_gso_max_size(netdev, 7 * 4096);

			h->dev->ops->set_tso_stats(h, 1);

		} else {

		} else {

			priv->ops.fill_desc = fill_v2_desc;

			priv->ops.fill_desc = fill_v2_desc;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tx;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tx;

			h->dev->ops->set_tso_stats(h, 0);

		}

		}

		break;

		break;

	}

	}
@@ -1804,11 +1801,14 @@ static void hns_nic_set_priv_ops(struct net_device *netdev) 
			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tso;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tso;

			/* This chip only support 7*4096 */

			/* This chip only support 7*4096 */

			netif_set_gso_max_size(netdev, 7 * 4096);

			netif_set_gso_max_size(netdev, 7 * 4096);

			h->dev->ops->set_tso_stats(h, 1);

		} else {

		} else {

			priv->ops.fill_desc = fill_v2_desc;

			priv->ops.fill_desc = fill_v2_desc;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tx;

			priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tx;

		}

		}

		/* enable tso when init

		 * control tso on/off through TSE bit in bd

		 */

		h->dev->ops->set_tso_stats(h, 1);

	}

	}

}

}