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Commit 6fd72492 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent 



The revision id range for this workaround has changed. So apply
it to all revids on all gen9.

References: HSD#2134449
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-6-git-send-email-mika.kuoppala@intel.com


(cherry picked from commit 5b0e3659)
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent 89b54515

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −7
Original line number Diff line number Diff line
@@ -913,7 +913,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
{

	struct drm_device *dev = engine->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t tmp;

	int ret;



	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
@@ -973,12 +972,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,

				  PIXEL_MASK_CAMMING_DISABLE);



	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */

	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;

	if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||

	    IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))

		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;

	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);

	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */

	WA_SET_BIT_MASKED(HDC_CHICKEN0,

			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |

			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);



	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */

	if (IS_SKYLAKE(dev_priv) ||