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Commit 6f98cb22 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Shawn Guo
Browse files

ARM: imx: remove cpu_is_mx1 check



There is only one call site for this, and it's easily replaced
by initializing the reset value at boot time.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 510aca64
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+1 −0
Original line number Original line Diff line number Diff line
@@ -54,6 +54,7 @@ struct platform_device *mxc_register_gpio(char *name, int id,
void mxc_set_cpu_type(unsigned int type);
void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *);
void mxc_arch_reset_init(void __iomem *);
void imx1_reset_init(void __iomem *);
void imx_set_aips(void __iomem *);
void imx_set_aips(void __iomem *);
void imx_aips_allow_unprivileged_access(const char *compat);
void imx_aips_allow_unprivileged_access(const char *compat);
int mxc_device_init(void);
int mxc_device_init(void);
+1 −1
Original line number Original line Diff line number Diff line
@@ -50,7 +50,7 @@ void __init mx1_init_irq(void)


void __init imx1_soc_init(void)
void __init imx1_soc_init(void)
{
{
	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
	imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
	mxc_device_init();
	mxc_device_init();


	mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
	mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
+9 −7
Original line number Original line Diff line number Diff line
@@ -34,25 +34,19 @@


static void __iomem *wdog_base;
static void __iomem *wdog_base;
static struct clk *wdog_clk;
static struct clk *wdog_clk;
static int wcr_enable = (1 << 2);


/*
/*
 * Reset the system. It is called by machine_restart().
 * Reset the system. It is called by machine_restart().
 */
 */
void mxc_restart(enum reboot_mode mode, const char *cmd)
void mxc_restart(enum reboot_mode mode, const char *cmd)
{
{
	unsigned int wcr_enable;

	if (!wdog_base)
	if (!wdog_base)
		goto reset_fallback;
		goto reset_fallback;


	if (!IS_ERR(wdog_clk))
	if (!IS_ERR(wdog_clk))
		clk_enable(wdog_clk);
		clk_enable(wdog_clk);


	if (cpu_is_mx1())
		wcr_enable = (1 << 0);
	else
		wcr_enable = (1 << 2);

	/* Assert SRS signal */
	/* Assert SRS signal */
	imx_writew(wcr_enable, wdog_base);
	imx_writew(wcr_enable, wdog_base);
	/*
	/*
@@ -89,6 +83,14 @@ void __init mxc_arch_reset_init(void __iomem *base)
		clk_prepare(wdog_clk);
		clk_prepare(wdog_clk);
}
}


#ifdef CONFIG_SOC_IMX1
void __init imx1_reset_init(void __iomem *base)
{
	wcr_enable = (1 << 0);
	mxc_arch_reset_init(base);
}
#endif

#ifdef CONFIG_CACHE_L2X0
#ifdef CONFIG_CACHE_L2X0
void __init imx_init_l2cache(void)
void __init imx_init_l2cache(void)
{
{