Merge tag 'mfd-for-linus-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

axp209 (X-Powers)

axp221 (X-Powers)

axp223 (X-Powers)

axp809 (X-Powers)

Required properties:

- compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",

	      "x-powers,axp221", "x-powers,axp223"

	      "x-powers,axp221", "x-powers,axp223", "x-powers,axp809"

- reg: The I2C slave address or RSB hardware address for the AXP chip

- interrupt-parent: The parent interrupt controller

- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin

Optional properties:

- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz

		      (range: 750-1875). Default: 1.5MHz

		      AXP152/20X: range:  750-1875, Default: 1.5 MHz

		      AXP22X/80X: range: 1800-4050, Default: 3   MHz

- <input>-supply: a phandle to the regulator supply node. May be omitted if

		  inputs are unregulated, such as using the IPSOUT output

		  from the PMIC.

LDO_IO1		: LDO		: ips-supply		: GPIO 1

RTC_LDO		: LDO		: ips-supply		: always on

AXP809 regulators, type, and corresponding input supply names:

Regulator	  Type		  Supply Name		  Notes

---------	  ----		  -----------		  -----

DCDC1		: DC-DC buck	: vin1-supply

DCDC2		: DC-DC buck	: vin2-supply

DCDC3		: DC-DC	buck	: vin3-supply

DCDC4		: DC-DC	buck	: vin4-supply

DCDC5		: DC-DC	buck	: vin5-supply

DC1SW		: On/Off Switch	:			: DCDC1 secondary output

DC5LDO		: LDO		:			: input from DCDC5

ALDO1		: LDO		: aldoin-supply		: shared supply

ALDO2		: LDO		: aldoin-supply		: shared supply

ALDO3		: LDO		: aldoin-supply		: shared supply

DLDO1		: LDO		: dldoin-supply		: shared supply

DLDO2		: LDO		: dldoin-supply		: shared supply

ELDO1		: LDO		: eldoin-supply		: shared supply

ELDO2		: LDO		: eldoin-supply		: shared supply

ELDO3		: LDO		: eldoin-supply		: shared supply

LDO_IO0		: LDO		: ips-supply		: GPIO 0

LDO_IO1		: LDO		: ips-supply		: GPIO 1

RTC_LDO		: LDO		: ips-supply		: always on

SW		: On/Off Switch : swin-supply

Example:

axp209: pmic@34 {

Hisilicon Hi655x Power Management Integrated Circuit (PMIC)

The hardware layout for access PMIC Hi655x from AP SoC Hi6220.

Between PMIC Hi655x and Hi6220, the physical signal channel is SSI.

We can use memory-mapped I/O to communicate.

+----------------+             +-------------+

|                |             |             |

|    Hi6220      |   SSI bus   |   Hi655x    |

|                |-------------|             |

|                |(REGMAP_MMIO)|             |

+----------------+             +-------------+

Required properties:

- compatible:           Should be "hisilicon,hi655x-pmic".

- reg:                  Base address of PMIC on Hi6220 SoC.

- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).

- pmic-gpios:           The GPIO used by PMIC IRQ.

Example:

	pmic: pmic@f8000000 {

		compatible = "hisilicon,hi655x-pmic";

		reg = <0x0 0xf8000000 0x0 0x1000>;

		interrupt-controller;

		#interrupt-cells = <2>;

		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;

	}

MAX77620 Power management IC from Maxim Semiconductor.

Required properties:

-------------------

- compatible: Must be one of

		"maxim,max77620"

		"maxim,max20024".

- reg: I2C device address.

Optional properties:

-------------------

- interrupts:		The interrupt on the parent the controller is

			connected to.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells:	is <2> and their usage is compliant to the 2 cells

			variant of <../interrupt-controller/interrupts.txt>

			IRQ numbers for different interrupt source of MAX77620

			are defined at dt-bindings/mfd/max77620.h.

Optional subnodes and their properties:

=======================================

Flexible power sequence configurations:

--------------------------------------

The Flexible Power Sequencer (FPS) allows each regulator to power up under

hardware or software control. Additionally, each regulator can power on

independently or among a group of other regulators with an adjustable power-up

and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed

to be part of a sequence allowing external regulators to be sequenced along

with internal regulators. 32KHz clock can be programmed to be part of a

sequence.

The flexible sequencing structure consists of two hardware enable inputs

(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.

Each master sequencing timer is programmable through its configuration

register to have a hardware enable source (EN1 or EN2) or a software enable

source (SW). When enabled/disabled, the master sequencing timer generates

eight sequencing events on different time periods called slots. The time

period between each event is programmable within the configuration register.

Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power

sequence slave register which allows its enable source to be specified as

a flexible power sequencer timer or a software bit. When a FPS source of

regulators, GPIOs and clocks specifies the enable source to be a flexible

power sequencer, the power up and power down delays can be specified in

the regulators, GPIOs and clocks flexible power sequencer configuration

registers.

When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz

clock are set into following state at the sequencing event that

corresponds to its flexible sequencer configuration register.

	Sleep state: 			In this state, regulators, GPIOs

					and 32KHz clock get disabled at

					the sequencing event.

	Global Low Power Mode (GLPM):	In this state, regulators are set in

					low power mode at the sequencing event.

The configuration parameters of FPS is provided through sub-node "fps"

and their child for FPS specific. The child node name for FPS are "fps0",

"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.

The FPS configurations like FPS source, power up and power down slots for

regulators, GPIOs and 32kHz clocks are provided in their respective

configuration nodes which is explained in respective sub-system DT

binding document.

There is need for different FPS configuration parameters based on system

state like when system state changed from active to suspend or active to

power off (shutdown).

Optional properties:

-------------------

-maxim,fps-event-source:		u32, FPS event source like external

					hardware input to PMIC i.e. EN0, EN1 or

					software (SW).

					The macros are defined on

						dt-bindings/mfd/max77620.h

					for different control source.

					- MAX77620_FPS_EVENT_SRC_EN0

						for hardware input pin EN0.

					- MAX77620_FPS_EVENT_SRC_EN1

						for hardware input pin EN1.

					- MAX77620_FPS_EVENT_SRC_SW

						for software control.

-maxim,shutdown-fps-time-period-us:	u32, FPS time period in microseconds

					when system enters in to shutdown

					state.

-maxim,suspend-fps-time-period-us:	u32, FPS time period in microseconds

					when system enters in to suspend state.

-maxim,device-state-on-disabled-event:	u32, describe the PMIC state when FPS

					event cleared (set to LOW) whether it

					should go to sleep state or low-power

					state. Following are valid values:

					- MAX77620_FPS_INACTIVE_STATE_SLEEP

						to set the PMIC state to sleep.

					- MAX77620_FPS_INACTIVE_STATE_LOW_POWER

						to set the PMIC state to low

						power.

					Absence of this property or other value

					will not change device state when FPS

					event get cleared.

Here supported time periods by device in microseconds are as follows:

MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.

MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.

For DT binding details of different sub modules like GPIO, pincontrol,

regulator, power, please refer respective device-tree binding document

under their respective sub-system directories.

Example:

--------

#include <dt-bindings/mfd/max77620.h>

max77620@3c {

	compatible = "maxim,max77620";

	reg = <0x3c>;

	interrupt-parent = <&intc>;

	interrupts = <0 86 IRQ_TYPE_NONE>;

	interrupt-controller;

	#interrupt-cells = <2>;

	fps {

		fps0 {

			maxim,shutdown-fps-time-period-us = <1280>;

			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;

		};

		fps1 {

			maxim,shutdown-fps-time-period-us = <1280>;

			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;

		};

		fps2 {

			maxim,shutdown-fps-time-period-us = <1280>;

			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;

		};

	};

};

  devm_kvasprintf()

  devm_kzalloc()

MFD

 devm_mfd_add_devices()

PCI

  pcim_enable_device()	: after success, all PCI ops become managed

  pcim_pin_device()	: keep PCI device enabled after release

F:	kernel/workqueue.c

F:	Documentation/workqueue.txt

X-POWERS MULTIFUNCTION PMIC DEVICE DRIVERS

M:	Chen-Yu Tsai <wens@csie.org>

L:	linux-kernel@vger.kernel.org

S:	Maintained

N:	axp[128]

X.25 NETWORK LAYER

M:	Andrew Hendry <andrew.hendry@gmail.com>

L:	linux-x25@vger.kernel.org