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Commit 6e037fb7 authored by Anurag Kumar Vulisha's avatar Anurag Kumar Vulisha Committed by Tejun Heo
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ata: ceva: Correct the AXI bus configuration for SATA ports 



Previously PAXIC register was programmed before configuring PCFG
register. PCFG should be programmed with the address of the port
for which PAXIC should be configured for.
This was not happening before, so only one port PAXIC was written
correctly and the other port was having wrong value.
This patch moves the PXAIC register write after configuring PCFG,
doing so will correct the axi bus settings for sata port0 & port1.

Signed-off-by: default avatarAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent 3bc867de

drivers/ata/ahci_ceva.c

+8 −8
Original line number Diff line number Diff line
@@ -134,14 +134,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv) 
	u32 tmp;

	int i;



	/*

	 * AXI Data bus width to 64

	 * Set Mem Addr Read, Write ID for data transfers

	 * Transfer limit to 72 DWord

	 */

	tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;

	writel(tmp, mmio + AHCI_VEND_PAXIC);



	/* Set AHCI Enable */

	tmp = readl(mmio + HOST_CTL);

	tmp |= HOST_AHCI_EN;
@@ -152,6 +144,14 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv) 
		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);

		writel(tmp, mmio + AHCI_VEND_PCFG);



		/*

		 * AXI Data bus width to 64

		 * Set Mem Addr Read, Write ID for data transfers

		 * Transfer limit to 72 DWord

		 */

		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;

		writel(tmp, mmio + AHCI_VEND_PAXIC);



		/* Set AXI cache control register if CCi is enabled */

		if (cevapriv->is_cci_enabled) {

			tmp = readl(mmio + AHCI_VEND_AXICC);