Commit 6deac6f2 authored Oct 05, 2009 by Alexander Duyck Committed by David S. Miller Oct 06, 2009

igb: add flushes between RAR writes when setting mac address



There are some switches that will do write combining when they see two
sequential regions written. In order to avoid any possible write combining
issues it is necessary to add a flush after writing each piece of a rar
register.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 2553bb26

drivers/net/igb/e1000_mac.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -247,8 +247,15 @@ void igb_rar_set(struct e1000_hw hw, u8 addr, u32 index)
		if (rar_low \|\| rar_high)
		rar_high \|= E1000_RAH_AV;

		/*
		* Some bridges will combine consecutive 32-bit writes into
		* a single burst write, which will malfunction on some parts.
		* The flushes avoid this.
		*/
		wr32(E1000_RAL(index), rar_low);
		wrfl();
		wr32(E1000_RAH(index), rar_high);
		wrfl();
		}

		/**