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Commit 6cc40834 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-tm-fixes' 



Yunsheng Lin says:

====================
TM related bugfixes for the HNS3 Ethernet Driver

This patch set contains a few bugfixes related to hclge_tm module.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4c4d11b9 c5795c53

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+13 −2
Original line number Diff line number Diff line
@@ -49,7 +49,17 @@ 
#define HNAE3_CLASS_NAME_SIZE 16



#define HNAE3_DEV_INITED_B			0x0

#define HNAE_DEV_SUPPORT_ROCE_B			0x1

#define HNAE3_DEV_SUPPORT_ROCE_B		0x1

#define HNAE3_DEV_SUPPORT_DCB_B			0x2



#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\

		BIT(HNAE3_DEV_SUPPORT_ROCE_B))



#define hnae3_dev_roce_supported(hdev) \

	hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)



#define hnae3_dev_dcb_supported(hdev) \

	hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)



#define ring_ptr_move_fw(ring, p) \

	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
@@ -366,12 +376,12 @@ struct hnae3_ae_algo { 
struct hnae3_tc_info {

	u16	tqp_offset;	/* TQP offset from base TQP */

	u16	tqp_count;	/* Total TQPs */

	u8	up;		/* user priority */

	u8	tc;		/* TC index */

	bool	enable;		/* If this TC is enable or not */

};



#define HNAE3_MAX_TC		8

#define HNAE3_MAX_USER_PRIO	8

struct hnae3_knic_private_info {

	struct net_device *netdev; /* Set by KNIC client when init instance */

	u16 rss_size;		   /* Allocated RSS queues */
@@ -379,6 +389,7 @@ struct hnae3_knic_private_info { 
	u16 num_desc;



	u8 num_tc;		   /* Total number of enabled TCs */

	u8 prio_tc[HNAE3_MAX_USER_PRIO];  /* TC indexed by prio */

	struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */



	u16 num_tqps;		  /* total number of TQPs in this handle */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+3 −1
Original line number Diff line number Diff line
@@ -270,7 +270,8 @@ struct hclge_tx_buff_alloc { 


struct hclge_rx_priv_buff {

	__le16 buf_num[HCLGE_TC_NUM];

	u8 rsv[8];

	__le16 shared_buf;

	u8 rsv[6];

};



struct hclge_query_version {
@@ -688,6 +689,7 @@ struct hclge_reset_tqp_queue { 
#define HCLGE_DEFAULT_TX_BUF		0x4000	 /* 16k  bytes */

#define HCLGE_TOTAL_PKT_BUF		0x108000 /* 1.03125M bytes */

#define HCLGE_DEFAULT_DV		0xA000	 /* 40k byte */

#define HCLGE_DEFAULT_NON_DCB_DV	0x7800	/* 30K byte */



#define HCLGE_TYPE_CRQ			0

#define HCLGE_TYPE_CSQ			1

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+88 −75
Original line number Diff line number Diff line
@@ -46,17 +46,7 @@ static const struct pci_device_id ae_algo_pci_tbl[] = { 
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},

	/* Required last entry */

	{0, }

};



static const struct pci_device_id roce_pci_tbl[] = {

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},

	/* Required last entry */

	/* required last entry */

	{0, }

};
@@ -894,7 +884,7 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) 
	hdev->num_tqps = __le16_to_cpu(req->tqp_num);

	hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;



	if (hnae_get_bit(hdev->ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B)) {

	if (hnae3_dev_roce_supported(hdev)) {

		hdev->num_roce_msix =

		hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),

			       HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
@@ -1454,7 +1444,11 @@ static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all) 
	tc_num = hclge_get_tc_num(hdev);

	pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);



	if (hnae3_dev_dcb_supported(hdev))

		shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;

	else

		shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;



	shared_buf_tc = pfc_enable_num * hdev->mps +

			(tc_num - pfc_enable_num) * hdev->mps / 2 +

			hdev->mps;
@@ -1495,6 +1489,16 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) 
	struct hclge_priv_buf *priv;

	int i;



	/* When DCB is not supported, rx private

	 * buffer is not allocated.

	 */

	if (!hnae3_dev_dcb_supported(hdev)) {

		if (!hclge_is_rx_buf_ok(hdev, rx_all))

			return -ENOMEM;



		return 0;

	}



	/* step 1, try to alloc private buffer for all enabled tc */

	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {

		priv = &hdev->priv_buf[i];
@@ -1510,6 +1514,11 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) 
				priv->wl.high = 2 * hdev->mps;

				priv->buf_size = priv->wl.high;

			}

		} else {

			priv->enable = 0;

			priv->wl.low = 0;

			priv->wl.high = 0;

			priv->buf_size = 0;

		}

	}
@@ -1522,7 +1531,14 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) 
	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {

		priv = &hdev->priv_buf[i];



		if (hdev->hw_tc_map & BIT(i))

		priv->enable = 0;

		priv->wl.low = 0;

		priv->wl.high = 0;

		priv->buf_size = 0;



		if (!(hdev->hw_tc_map & BIT(i)))

			continue;



		priv->enable = 1;



		if (hdev->tm_info.hw_pfc_map & BIT(i)) {
@@ -1616,6 +1632,10 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev) 
			cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);

	}



	req->shared_buf =

		cpu_to_le16((hdev->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |

			    (1 << HCLGE_TC0_PRI_BUF_EN_B));



	ret = hclge_cmd_send(&hdev->hw, &desc, 1);

	if (ret) {

		dev_err(&hdev->pdev->dev,
@@ -1782,19 +1802,23 @@ int hclge_buffer_alloc(struct hclge_dev *hdev) 
		return ret;

	}



	if (hnae3_dev_dcb_supported(hdev)) {

		ret = hclge_rx_priv_wl_config(hdev);

		if (ret) {

			dev_err(&hdev->pdev->dev,

			"could not configure rx private waterline %d\n", ret);

				"could not configure rx private waterline %d\n",

				ret);

			return ret;

		}



		ret = hclge_common_thrd_config(hdev);

		if (ret) {

			dev_err(&hdev->pdev->dev,

			"could not configure common threshold %d\n", ret);

				"could not configure common threshold %d\n",

				ret);

			return ret;

		}

	}



	ret = hclge_common_wl_config(hdev);

	if (ret) {
@@ -2582,6 +2606,7 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) 
	u16 tc_valid[HCLGE_MAX_TC_NUM];

	u16 tc_size[HCLGE_MAX_TC_NUM];

	u32 *rss_indir = NULL;

	u16 rss_size = 0, roundup_size;

	const u8 *key;

	int i, ret, j;
@@ -2596,7 +2621,13 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) 
	for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {

		for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {

			vport[j].rss_indirection_tbl[i] =

				i % hdev->rss_size_max;

				i % vport[j].alloc_rss_size;



			/* vport 0 is for PF */

			if (j != 0)

				continue;



			rss_size = vport[j].alloc_rss_size;

			rss_indir[i] = vport[j].rss_indirection_tbl[i];

		}

	}
@@ -2613,42 +2644,31 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) 
	if (ret)

		goto err;



	/* Each TC have the same queue size, and tc_size set to hardware is

	 * the log2 of roundup power of two of rss_size, the acutal queue

	 * size is limited by indirection table.

	 */

	if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {

		dev_err(&hdev->pdev->dev,

			"Configure rss tc size failed, invalid TC_SIZE = %d\n",

			rss_size);

		return -EINVAL;

	}



	roundup_size = roundup_pow_of_two(rss_size);

	roundup_size = ilog2(roundup_size);



	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {

		if (hdev->hw_tc_map & BIT(i))

			tc_valid[i] = 1;

		else

		tc_valid[i] = 0;



		switch (hdev->rss_size_max) {

		case HCLGE_RSS_TC_SIZE_0:

			tc_size[i] = 0;

			break;

		case HCLGE_RSS_TC_SIZE_1:

			tc_size[i] = 1;

			break;

		case HCLGE_RSS_TC_SIZE_2:

			tc_size[i] = 2;

			break;

		case HCLGE_RSS_TC_SIZE_3:

			tc_size[i] = 3;

			break;

		case HCLGE_RSS_TC_SIZE_4:

			tc_size[i] = 4;

			break;

		case HCLGE_RSS_TC_SIZE_5:

			tc_size[i] = 5;

			break;

		case HCLGE_RSS_TC_SIZE_6:

			tc_size[i] = 6;

			break;

		case HCLGE_RSS_TC_SIZE_7:

			tc_size[i] = 7;

			break;

		default:

			break;

		}

		tc_offset[i] = hdev->rss_size_max * i;

		if (!(hdev->hw_tc_map & BIT(i)))

			continue;



		tc_valid[i] = 1;

		tc_size[i] = roundup_size;

		tc_offset[i] = rss_size * i;

	}



	ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);



err:
@@ -3932,8 +3952,7 @@ static int hclge_init_client_instance(struct hnae3_client *client, 
				goto err;



			if (hdev->roce_client &&

			    hnae_get_bit(hdev->ae_dev->flag,

					 HNAE_DEV_SUPPORT_ROCE_B)) {

			    hnae3_dev_roce_supported(hdev)) {

				struct hnae3_client *rc = hdev->roce_client;



				ret = hclge_init_roce_base_info(vport);
@@ -3956,8 +3975,7 @@ static int hclge_init_client_instance(struct hnae3_client *client, 


			break;

		case HNAE3_CLIENT_ROCE:

			if (hnae_get_bit(hdev->ae_dev->flag,

					 HNAE_DEV_SUPPORT_ROCE_B)) {

			if (hnae3_dev_roce_supported(hdev)) {

				hdev->roce_client = client;

				vport->roce.client = client;

			}
@@ -4069,7 +4087,6 @@ static void hclge_pci_uninit(struct hclge_dev *hdev) 
static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)

{

	struct pci_dev *pdev = ae_dev->pdev;

	const struct pci_device_id *id;

	struct hclge_dev *hdev;

	int ret;
@@ -4084,10 +4101,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 
	hdev->ae_dev = ae_dev;

	ae_dev->priv = hdev;



	id = pci_match_id(roce_pci_tbl, ae_dev->pdev);

	if (id)

		hnae_set_bit(ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B, 1);



	ret = hclge_pci_init(hdev);

	if (ret) {

		dev_err(&pdev->dev, "PCI init failed\n");
@@ -4150,12 +4163,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 
		return ret;

	}



	ret = hclge_rss_init_hw(hdev);

	if (ret) {

		dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);

		return  ret;

	}



	ret = hclge_init_vlan_config(hdev);

	if (ret) {

		dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
@@ -4168,6 +4175,12 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 
		return ret;

	}



	ret = hclge_rss_init_hw(hdev);

	if (ret) {

		dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);

		return ret;

	}



	setup_timer(&hdev->service_timer, hclge_service_timer,

		    (unsigned long)hdev);

	INIT_WORK(&hdev->service_task, hclge_service_task);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+2 −1
Original line number Diff line number Diff line
@@ -176,7 +176,6 @@ struct hclge_pg_info { 
struct hclge_tc_info {

	u8 tc_id;

	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */

	u8 up;

	u8 pgid;

	u32 bw_limit;

};
@@ -197,6 +196,7 @@ struct hclge_tm_info { 
	u8 num_tc;

	u8 num_pg;      /* It must be 1 if vNET-Base schd */

	u8 pg_dwrr[HCLGE_PG_NUM];

	u8 prio_tc[HNAE3_MAX_USER_PRIO];

	struct hclge_pg_info pg_info[HCLGE_PG_NUM];

	struct hclge_tc_info tc_info[HNAE3_MAX_TC];

	enum hclge_fc_mode fc_mode;
@@ -477,6 +477,7 @@ struct hclge_vport { 
	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */

	/* User configured lookup table entries */

	u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];

	u16 alloc_rss_size;



	u16 qs_offset;

	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

+24 −17
Original line number Diff line number Diff line
@@ -128,9 +128,7 @@ static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 
{

	u8 tc;



	for (tc = 0; tc < hdev->tm_info.num_tc; tc++)

		if (hdev->tm_info.tc_info[tc].up == pri_id)

			break;

	tc = hdev->tm_info.prio_tc[pri_id];



	if (tc >= hdev->tm_info.num_tc)

		return -EINVAL;
@@ -158,7 +156,7 @@ static int hclge_up_to_tc_map(struct hclge_dev *hdev) 


	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);



	for (pri_id = 0; pri_id < hdev->tm_info.num_tc; pri_id++) {

	for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {

		ret = hclge_fill_pri_array(hdev, pri, pri_id);

		if (ret)

			return ret;
@@ -280,11 +278,11 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pg_id = pg_id;



	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);

	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);

	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);

	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);

	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}
@@ -307,11 +305,11 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pri_id = pri_id;



	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);

	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);

	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);

	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);

	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}
@@ -397,6 +395,7 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 
			kinfo->num_tqps / kinfo->num_tc);

	vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id;

	vport->dwrr = 100;  /* 100 percent as init */

	vport->alloc_rss_size = kinfo->rss_size;



	for (i = 0; i < kinfo->num_tc; i++) {

		if (hdev->hw_tc_map & BIT(i)) {
@@ -404,16 +403,17 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 
			kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;

			kinfo->tc_info[i].tqp_count = kinfo->rss_size;

			kinfo->tc_info[i].tc = i;

			kinfo->tc_info[i].up = hdev->tm_info.tc_info[i].up;

		} else {

			/* Set to default queue if TC is disable */

			kinfo->tc_info[i].enable = false;

			kinfo->tc_info[i].tqp_offset = 0;

			kinfo->tc_info[i].tqp_count = 1;

			kinfo->tc_info[i].tc = 0;

			kinfo->tc_info[i].up = 0;

		}

	}



	memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,

	       FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));

}



static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
@@ -435,12 +435,15 @@ static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 
	for (i = 0; i < hdev->tm_info.num_tc; i++) {

		hdev->tm_info.tc_info[i].tc_id = i;

		hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;

		hdev->tm_info.tc_info[i].up = i;

		hdev->tm_info.tc_info[i].pgid = 0;

		hdev->tm_info.tc_info[i].bw_limit =

			hdev->tm_info.pg_info[0].bw_limit;

	}



	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)

		hdev->tm_info.prio_tc[i] =

			(i >= hdev->tm_info.num_tc) ? 0 : i;



	hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;

}
@@ -976,6 +979,10 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev) 
	if (ret)

		return ret;



	/* Only DCB-supported dev supports qset back pressure setting */

	if (!hnae3_dev_dcb_supported(hdev))

		return 0;



	for (i = 0; i < hdev->tm_info.num_tc; i++) {

		ret = hclge_tm_qs_bp_cfg(hdev, i);

		if (ret)