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Commit 6bb62855 authored Jun 06, 2016 by arun.siluvery@linux.intel.com Committed by Tvrtko Ursulin Jun 06, 2016

drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear



Kernel only need to add a register to HW whitelist, required for a
preemption related issue.

Reference: HSD#2131039
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465203169-16591-1-git-send-email-arun.siluvery@linux.intel.com

parent 14bb2c11

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
		#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)

		#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
		#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
		#define GEN8_CS_CHICKEN1 _MMIO(0x2580)

		/* GEN7 chicken */

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
		I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) \|
		GEN8_LQSC_FLUSH_COHERENT_LINES));

		/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
		ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
		if (ret)
		return ret;

		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
		ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
		if (ret)