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Commit 6ba844b0 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: GEN7_MSG_CONTROL is ivb-only 



At least I couldn't find it in the Haswell Bspec any more and we've
tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
hit the PCH_NOP path) and the unclaimed register logic complained.

So restrict this dance to just ivb platforms.

v2: Art pointed out that the bits simply moved on hsw+

v3: Buy code terseneness with a notch of sublety as suggested by
Chris.

v4: Frob the right bit, spotted by Art.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Reviewed-by: default avatarArt Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d34ff9c6

drivers/gpu/drm/i915/i915_gem.c

+9 −3
Original line number Original line Diff line number Diff line
@@ -4471,9 +4471,15 @@ i915_gem_init_hw(struct drm_device *dev) 
			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);

			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);





	if (HAS_PCH_NOP(dev)) {

	if (HAS_PCH_NOP(dev)) {

		if (IS_IVYBRIDGE(dev)) {

			u32 temp = I915_READ(GEN7_MSG_CTL);

			u32 temp = I915_READ(GEN7_MSG_CTL);

			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

			I915_WRITE(GEN7_MSG_CTL, temp);

			I915_WRITE(GEN7_MSG_CTL, temp);

		} else if (INTEL_INFO(dev)->gen >= 7) {

			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);

			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;

			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);

		}

	}

	}





	i915_gem_init_swizzling(dev);

	i915_gem_init_swizzling(dev);

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -4119,6 +4119,8 @@ 
#define GEN7_MSG_CTL	0x45010

#define GEN7_MSG_CTL	0x45010

#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)

#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)

#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)

#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)

#define HSW_NDE_RSTWRN_OPT	0x46408

#define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)





/* GEN7 chicken */

/* GEN7 chicken */

#define GEN7_COMMON_SLICE_CHICKEN1		0x7010

#define GEN7_COMMON_SLICE_CHICKEN1		0x7010