Commit 6b2f1351 authored Feb 27, 2018 by Sinan Kaya Committed by Bjorn Helgaas Mar 05, 2018

PCI: Wait for device to become ready after secondary bus reset



Setting Secondary Bus Reset of a downstream port sends a hot reset.  PCIe
r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can return
CRS Completion Status following such a reset.  Wait until the device
becomes ready in that situation.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>

parent 01fd61c0

drivers/pci/pci.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -4233,7 +4233,7 @@ int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
		{
		pcibios_reset_secondary_bus(dev);

		return 0;
		return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
		}
		EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);