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Commit 6ad4cc8d authored by Andre Przywara's avatar Andre Przywara Committed by Linus Walleij
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pinctrl: sunxi: Fix A80 interrupt pin bank 



On the A80 the pins on port B can trigger interrupts, and those are
assigned to the second interrupt bank.
Having two pins assigned to the same interrupt bank/pin combination does
not look healthy (instead more like a copy&paste bug from pins PA14-PA16),
so fix the interrupt bank for pins PB14-PB16, which is actually 1.

I don't have any A80 board, so could not test this.

Fixes: d5e9fb31 ("pinctrl: sunxi: Add A80 pinctrl muxing options")
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 793b9184

drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

+3 −3
Original line number Diff line number Diff line
@@ -145,19 +145,19 @@ static const struct sunxi_desc_pin sun9i_a80_pins[] = { 
		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x3, "mcsi"),		/* MCLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),	/* PB_EINT14 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),	/* PB_EINT14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x3, "mcsi"),		/* SCK */

		  SUNXI_FUNCTION(0x4, "i2c4"),		/* SCK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),	/* PB_EINT15 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),	/* PB_EINT15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x3, "mcsi"),		/* SDA */

		  SUNXI_FUNCTION(0x4, "i2c4"),		/* SDA */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),	/* PB_EINT16 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),	/* PB_EINT16 */



	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),