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Commit 6887765e authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Greg Kroah-Hartman
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clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks 



commit 72cfd1ad1057f16fc614861b3c271597995e57ba upstream.

STM32MP1 clock IP offers lots of Kernel clocks that are shared
by multiple IP's at the same time.
Then boot loader applies a clock tree that allows to use all IP's
at same time and with the maximum of performance.
Not change parents on a change rate on kernel clocks ensures
the integrity of the system.

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8b4c3653

drivers/clk/clk-stm32mp1.c

+7 −5
Original line number Diff line number Diff line
@@ -1286,7 +1286,8 @@ _clk_stm32_register_composite(struct device *dev, 
	MGATE_MP1(_id, _name, _parent, _flags, _mgate)



#define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\

	     COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\

	     COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\

		       CLK_SET_RATE_NO_REPARENT | _flags,\

		       _MGATE_MP1(_mgate),\

		       _MMUX(_mmux),\

		       _NO_DIV)
@@ -1952,7 +1953,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = { 
	MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),

	MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),



	COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,

	COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |

		  CLK_SET_RATE_NO_REPARENT,

		  _NO_GATE,

		  _MMUX(M_ETHCK),

		  _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),