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Commit 67d1c0a2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux into drm-next 

This pull request fixes the major VC4 HDMI modesetting bugs found when
the first wave of users showed up in Raspbian.

* tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux:
  drm/vc4: Initialize scaler DISPBKGND on modeset.
  drm/vc4: Fix setting of vertical timings in the CRTC.
  drm/vc4: Fix the name of the VSYNCD_EVEN register.
  drm/vc4: Add another reg to HDMI debug dumping.
  drm/vc4: Bring HDMI up from power off if necessary.
  drm/vc4: Fix a framebuffer reference leak on async flip interrupt.
parents c3d7a1d1 6a609209

drivers/gpu/drm/vc4/vc4_crtc.c

+18 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static const struct { 
} crtc_regs[] = {

	CRTC_REG(PV_CONTROL),

	CRTC_REG(PV_V_CONTROL),

	CRTC_REG(PV_VSYNCD),

	CRTC_REG(PV_VSYNCD_EVEN),

	CRTC_REG(PV_HORZA),

	CRTC_REG(PV_HORZB),

	CRTC_REG(PV_VERTA),
@@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct drm_crtc *crtc) 


static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

	struct drm_crtc_state *state = crtc->state;

	struct drm_display_mode *mode = &state->adjusted_mode;
@@ -217,6 +219,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 
				 PV_HORZB_HFP) |

		   VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));



	CRTC_WRITE(PV_VERTA,

		   VC4_SET_FIELD(mode->vtotal - mode->vsync_end,

				 PV_VERTA_VBP) |

		   VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,

				 PV_VERTA_VSYNC));

	CRTC_WRITE(PV_VERTB,

		   VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,

				 PV_VERTB_VFP) |

		   VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));



	if (interlace) {

		CRTC_WRITE(PV_VERTA_EVEN,

			   VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
@@ -246,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 
		   PV_CONTROL_FIFO_CLR |

		   PV_CONTROL_EN);



	HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),

		  SCALER_DISPBKGND_AUTOHS |

		  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));



	if (debug_dump_regs) {

		DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));

		vc4_crtc_dump_regs(vc4_crtc);
@@ -527,6 +543,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, 
	/* Make sure all other async modesetes have landed. */

	ret = down_interruptible(&vc4->async_modeset);

	if (ret) {

		drm_framebuffer_unreference(fb);

		kfree(flip_state);

		return ret;

	}

drivers/gpu/drm/vc4/vc4_hdmi.c

+29 −1
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ static const struct { 
	HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),

	HDMI_REG(VC4_HDMI_HOTPLUG_INT),

	HDMI_REG(VC4_HDMI_HOTPLUG),

	HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),

	HDMI_REG(VC4_HDMI_HORZA),

	HDMI_REG(VC4_HDMI_HORZB),

	HDMI_REG(VC4_HDMI_FIFO_CTL),
@@ -495,6 +496,16 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 
		goto err_put_i2c;

	}



	/* This is the rate that is set by the firmware.  The number

	 * needs to be a bit higher than the pixel clock rate

	 * (generally 148.5Mhz).

	 */

	ret = clk_set_rate(hdmi->hsm_clock, 163682864);

	if (ret) {

		DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);

		goto err_unprepare_pix;

	}



	ret = clk_prepare_enable(hdmi->hsm_clock);

	if (ret) {

		DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
@@ -516,7 +527,24 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 
	vc4->hdmi = hdmi;



	/* HDMI core must be enabled. */

	WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);

	if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {

		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);

		udelay(1);

		HD_WRITE(VC4_HD_M_CTL, 0);



		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);



		HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,

			   VC4_HDMI_SW_RESET_HDMI |

			   VC4_HDMI_SW_RESET_FORMAT_DETECT);



		HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);



		/* PHY should be in reset, like

		 * vc4_hdmi_encoder_disable() does.

		 */

		HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);

	}



	drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,

			 DRM_MODE_ENCODER_TMDS, NULL);

drivers/gpu/drm/vc4/vc4_regs.h

+17 −1
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ 
# define PV_VCONTROL_CONTINUOUS			BIT(1)

# define PV_VCONTROL_VIDEN			BIT(0)



#define PV_VSYNCD				0x08

#define PV_VSYNCD_EVEN				0x08



#define PV_HORZA				0x0c

# define PV_HORZA_HBP_MASK			VC4_MASK(31, 16)
@@ -350,6 +350,17 @@ 
# define SCALER_DISPCTRLX_HEIGHT_SHIFT		0



#define SCALER_DISPBKGND0                       0x00000044

# define SCALER_DISPBKGND_AUTOHS		BIT(31)

# define SCALER_DISPBKGND_INTERLACE		BIT(30)

# define SCALER_DISPBKGND_GAMMA			BIT(29)

# define SCALER_DISPBKGND_TESTMODE_MASK		VC4_MASK(28, 25)

# define SCALER_DISPBKGND_TESTMODE_SHIFT	25

/* Enables filling the scaler line with the RGB value in the low 24

 * bits before compositing.  Costs cycles, so should be skipped if

 * opaque display planes will cover everything.

 */

# define SCALER_DISPBKGND_FILL			BIT(24)



#define SCALER_DISPSTAT0                        0x00000048

#define SCALER_DISPBASE0                        0x0000004c

# define SCALER_DISPSTATX_MODE_MASK		VC4_MASK(31, 30)
@@ -362,6 +373,9 @@ 
# define SCALER_DISPSTATX_EMPTY			BIT(28)

#define SCALER_DISPCTRL1                        0x00000050

#define SCALER_DISPBKGND1                       0x00000054

#define SCALER_DISPBKGNDX(x)			(SCALER_DISPBKGND0 +        \

						 (x) * (SCALER_DISPBKGND1 - \

							SCALER_DISPBKGND0))

#define SCALER_DISPSTAT1                        0x00000058

#define SCALER_DISPSTATX(x)			(SCALER_DISPSTAT0 +        \

						 (x) * (SCALER_DISPSTAT1 - \
@@ -456,6 +470,8 @@ 
#define VC4_HDMI_TX_PHY_RESET_CTL		0x2c0



#define VC4_HD_M_CTL				0x00c

# define VC4_HD_M_REGISTER_FILE_STANDBY		(3 << 6)

# define VC4_HD_M_RAM_STANDBY			(3 << 4)

# define VC4_HD_M_SW_RST			BIT(2)

# define VC4_HD_M_ENABLE			BIT(0)