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Commit 666a4537 authored by Wayne Boyer's avatar Wayne Boyer Committed by Daniel Vetter
Browse files

drm/i915: Separate cherryview from valleyview 



The cherryview device shares many characteristics with the valleyview
device.  When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.

This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.

v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
    Also add followup patches to fix issues discovered during the first
    review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
    as CRT is not supported on CHV. (Imre, Ville)
v4: Make a few more optimizations. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarWayne Boyer <wayne.boyer@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449692975-14803-1-git-send-email-wayne.boyer@intel.com


Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 825f2728

drivers/gpu/drm/i915/i915_debugfs.c

+34 −34
Original line number Diff line number Diff line
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
			   MEMSTAT_VID_SHIFT);

		seq_printf(m, "Current P-state: %d\n",

			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);

	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||

		   IS_BROADWELL(dev) || IS_GEN9(dev)) {

	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

		u32 freq_sts;



		mutex_lock(&dev_priv->rps.hw_lock);

		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);



		seq_printf(m, "actual GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));



		seq_printf(m, "current GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));



		seq_printf(m, "max GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));



		seq_printf(m, "min GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));



		seq_printf(m, "idle GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));



		seq_printf(m,

			   "efficient (RPe) frequency: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));

		mutex_unlock(&dev_priv->rps.hw_lock);

	} else if (INTEL_INFO(dev)->gen >= 6) {

		u32 rp_state_limits;

		u32 gt_perf_status;

		u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m,

			   "efficient (RPe) frequency: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));

	} else if (IS_VALLEYVIEW(dev)) {

		u32 freq_sts;



		mutex_lock(&dev_priv->rps.hw_lock);

		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);



		seq_printf(m, "actual GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));



		seq_printf(m, "current GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));



		seq_printf(m, "max GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));



		seq_printf(m, "min GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));



		seq_printf(m, "idle GPU freq: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));



		seq_printf(m,

			   "efficient (RPe) frequency: %d MHz\n",

			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));

		mutex_unlock(&dev_priv->rps.hw_lock);

	} else {

		seq_puts(m, "no P-state info available\n");

	}
@@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused) 
	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;



	if (IS_VALLEYVIEW(dev))

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		return vlv_drpc_info(m);

	else if (INTEL_INFO(dev)->gen >= 6)

		return gen6_drpc_info(m);
@@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) 
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;

	else if (IS_PINEVIEW(dev))

		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;

	else if (IS_VALLEYVIEW(dev))

	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;



	intel_runtime_pm_put(dev_priv);
@@ -3999,7 +3998,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
		ret = i8xx_pipe_crc_ctl_reg(&source, &val);

	else if (INTEL_INFO(dev)->gen < 5)

		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);

	else if (IS_VALLEYVIEW(dev))

	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);

	else if (IS_GEN5(dev) || IS_GEN6(dev))

		ret = ilk_pipe_crc_ctl_reg(&source, &val);
@@ -4068,7 +4067,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 


		if (IS_G4X(dev))

			g4x_undo_pipe_scramble_reset(dev, pipe);

		else if (IS_VALLEYVIEW(dev))

		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

			vlv_undo_pipe_scramble_reset(dev, pipe);

		else if (IS_HASWELL(dev) && pipe == PIPE_A)

			hsw_trans_edp_pipe_A_crc_wa(dev, false);
@@ -4458,7 +4457,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 
		 * - WM1+ latency values in 0.5us units

		 * - latencies are in us on gen9/vlv/chv

		 */

		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))

		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||

		    IS_CHERRYVIEW(dev))

			latency *= 10;

		else if (level > 0)

			latency *= 5;

drivers/gpu/drm/i915/i915_dma.c

+4 −7
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ intel_setup_mchbar(struct drm_device *dev) 
	u32 temp;

	bool enabled;



	if (IS_VALLEYVIEW(dev))

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		return;



	dev_priv->mchbar_need_disable = false;
@@ -782,7 +782,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) 
		info->num_sprites[PIPE_A] = 2;

		info->num_sprites[PIPE_B] = 2;

		info->num_sprites[PIPE_C] = 1;

	} else if (IS_VALLEYVIEW(dev))

	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		for_each_pipe(dev_priv, pipe)

			info->num_sprites[pipe] = 2;

	else
@@ -794,7 +794,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) 
		info->num_pipes = 0;

	} else if (info->num_pipes > 0 &&

		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&

		   !IS_VALLEYVIEW(dev)) {

		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {

		u32 fuse_strap = I915_READ(FUSE_STRAP);

		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
@@ -839,9 +839,6 @@ static void intel_device_info_runtime_init(struct drm_device *dev) 


static void intel_init_dpio(struct drm_i915_private *dev_priv)

{

	if (!IS_VALLEYVIEW(dev_priv))

		return;



	/*

	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),

	 * CHV x1 PHY (DP/HDMI D)
@@ -850,7 +847,7 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) 
	if (IS_CHERRYVIEW(dev_priv)) {

		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;

		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;

	} else {

	} else if (IS_VALLEYVIEW(dev_priv)) {

		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;

	}

}

drivers/gpu/drm/i915/i915_drv.c

+5 −5
Original line number Diff line number Diff line
@@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = { 
	.gen = 8, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.is_valleyview = 1,

	.is_cherryview = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	GEN_CHV_PIPEOFFSETS,

	CURSOR_OFFSETS,
@@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev) 


	pci_set_master(dev->pdev);



	if (IS_VALLEYVIEW(dev_priv))

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		ret = vlv_resume_prepare(dev_priv, false);

	if (ret)

		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
@@ -1533,7 +1533,7 @@ static int intel_runtime_resume(struct device *device) 
		ret = bxt_resume_prepare(dev_priv);

	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		hsw_disable_pc8(dev_priv);

	else if (IS_VALLEYVIEW(dev_priv))

	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		ret = vlv_resume_prepare(dev_priv, true);



	/*
@@ -1550,7 +1550,7 @@ static int intel_runtime_resume(struct device *device) 
	 * power well, so hpd is reinitialized from there. For

	 * everyone else do it here.

	 */

	if (!IS_VALLEYVIEW(dev_priv))

	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

		intel_hpd_init(dev_priv);



	intel_enable_gt_powersave(dev);
@@ -1575,7 +1575,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) 
		ret = bxt_suspend_complete(dev_priv);

	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		ret = hsw_suspend_complete(dev_priv);

	else if (IS_VALLEYVIEW(dev_priv))

	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		ret = vlv_suspend_complete(dev_priv);

	else

		ret = 0;

drivers/gpu/drm/i915/i915_drv.h

+10 −6
Original line number Diff line number Diff line
@@ -763,6 +763,7 @@ struct intel_csr { 
	func(is_crestline) sep \

	func(is_ivybridge) sep \

	func(is_valleyview) sep \

	func(is_cherryview) sep \

	func(is_haswell) sep \

	func(is_skylake) sep \

	func(is_broxton) sep \
@@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table { 
				 INTEL_DEVID(dev) == 0x0152 || \

				 INTEL_DEVID(dev) == 0x015a)

#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)

#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))

#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)

#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)

#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))

#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))

#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)

#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)

#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
@@ -2592,7 +2593,8 @@ struct drm_i915_cmd_table { 
				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))

#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \

				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \

				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))

				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \

				 IS_KABYLAKE(dev))

#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)

#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
@@ -2605,7 +2607,8 @@ struct drm_i915_cmd_table { 
				    INTEL_INFO(dev)->gen >= 8)



#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \

				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))

				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \

				 !IS_BROXTON(dev))



#define INTEL_PCH_DEVICE_ID_MASK		0xff00

#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
@@ -2628,7 +2631,8 @@ struct drm_i915_cmd_table { 
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)

#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)



#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))

#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \

			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))



/* DPF == dynamic parity feature */

#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
@@ -3521,7 +3525,7 @@ __raw_write(64, q) 


static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)

{

	if (IS_VALLEYVIEW(dev))

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		return VLV_VGACNTRL;

	else if (INTEL_INFO(dev)->gen >= 5)

		return CPU_VGACNTRL;

drivers/gpu/drm/i915/i915_gem.c

+2 −2
Original line number Diff line number Diff line
@@ -4854,7 +4854,7 @@ int i915_gem_init(struct drm_device *dev) 


	mutex_lock(&dev->struct_mutex);



	if (IS_VALLEYVIEW(dev)) {

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

		/* VLVA0 (potential hack), BIOS isn't actually waking us */

		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);

		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
@@ -4979,7 +4979,7 @@ i915_gem_load(struct drm_device *dev) 


	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;



	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))

	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))

		dev_priv->num_fence_regs = 32;

	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

		dev_priv->num_fence_regs = 16;