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Commit 66645656 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:
 "A few updates this time, most important and exiciting (to me) is:

   - The new ARM SMMU driver.  This is a common IOMMU driver that will
     hopefully be used in a lot of upcoming ARM chips.  So the mess in
     the past where every SOC had its own IOMMU will be over.

  Besides that:

   - Some important fixes in the IOMMU unmap path.  There are fixes in
     the common code and also in the AMD IOMMU driver.
   - Other random fixes"

* tag 'iommu-updates-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  MAINTAINERS: add entry for ARM system MMU driver
  iommu/arm: Add support for ARM Ltd. System MMU architecture
  documentation/iommu: Add description of ARM System MMU binding
  iommu: Use %pa and %zx instead of casting
  iommu/amd: Only unmap large pages from the first pte
  iommu: Fix compiler warning on pr_debug
  iommu/amd: Fix memory leak in free_pagetable
  iommu: Split iommu_unmaps
  iommu/{vt-d,amd}: Remove multifunction assumption around grouping
  iommu/omap: fix checkpatch warnings in omap iommu code
  iommu/omap: fix printk formats for dma_addr_t
  iommu/vt-d: DMAR reporting table needs at least one DRHD
  iommu/vt-d: Downgrade the warning if enabling irq remapping fails
parents 496fd15b 01ce784a

Documentation/devicetree/bindings/iommu/arm,smmu.txt

0 → 100644
+70 −0
Original line number Diff line number Diff line 
* ARM System MMU Architecture Implementation



ARM SoCs may contain an implementation of the ARM System Memory

Management Unit Architecture, which can be used to provide 1 or 2 stages

of address translation to bus masters external to the CPU.



The SMMU may also raise interrupts in response to various fault

conditions.



** System MMU required properties:



- compatible    : Should be one of:



                        "arm,smmu-v1"

                        "arm,smmu-v2"

                        "arm,mmu-400"

                        "arm,mmu-500"



                  depending on the particular implementation and/or the

                  version of the architecture implemented.



- reg           : Base address and size of the SMMU.



- #global-interrupts : The number of global interrupts exposed by the

                       device.



- interrupts    : Interrupt list, with the first #global-irqs entries

                  corresponding to the global interrupts and any

                  following entries corresponding to context interrupts,

                  specified in order of their indexing by the SMMU.



                  For SMMUv2 implementations, there must be exactly one

                  interrupt per context bank. In the case of a single,

                  combined interrupt, it must be listed multiple times.



- mmu-masters   : A list of phandles to device nodes representing bus

                  masters for which the SMMU can provide a translation

                  and their corresponding StreamIDs (see example below).

                  Each device node linked from this list must have a

                  "#stream-id-cells" property, indicating the number of

                  StreamIDs associated with it.



** System MMU optional properties:



- smmu-parent   : When multiple SMMUs are chained together, this

                  property can be used to provide a phandle to the

                  parent SMMU (that is the next SMMU on the path going

                  from the mmu-masters towards memory) node for this

                  SMMU.



Example:



        smmu {

                compatible = "arm,smmu-v1";

                reg = <0xba5e0000 0x10000>;

                #global-interrupts = <2>;

                interrupts = <0 32 4>,

                             <0 33 4>,

                             <0 34 4>, /* This is the first context interrupt */

                             <0 35 4>,

                             <0 36 4>,

                             <0 37 4>;



                /*

                 * Two DMA controllers, the first with two StreamIDs (0xd01d

                 * and 0xd01e) and the second with only one (0xd11c).

                 */

                mmu-masters = <&dma0 0xd01d 0xd01e>,

                              <&dma1 0xd11c>;

        };

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -1333,6 +1333,12 @@ S: Supported 
F:	arch/arm/mach-zynq/

F:	drivers/cpuidle/cpuidle-zynq.c



ARM SMMU DRIVER

M:	Will Deacon <will.deacon@arm.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/iommu/arm-smmu.c



ARM64 PORT (AARCH64 ARCHITECTURE)

M:	Catalin Marinas <catalin.marinas@arm.com>

M:	Will Deacon <will.deacon@arm.com>

drivers/iommu/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -269,4 +269,17 @@ config SPAPR_TCE_IOMMU 
	  Enables bits of IOMMU API required by VFIO. The iommu_ops

	  is not implemented as it is not necessary for VFIO.



config ARM_SMMU

	bool "ARM Ltd. System MMU (SMMU) Support"

	depends on ARM64 || (ARM_LPAE && OF)

	select IOMMU_API

	select ARM_DMA_USE_IOMMU if ARM

	help

	  Support for implementations of the ARM System MMU architecture

	  versions 1 and 2. The driver supports both v7l and v8l table

	  formats with 4k and 64k page sizes.



	  Say Y here if your SoC includes an IOMMU device implementing

	  the ARM SMMU architecture.



endif # IOMMU_SUPPORT

drivers/iommu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ obj-$(CONFIG_OF_IOMMU) += of_iommu.o 
obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o

obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o

obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o

obj-$(CONFIG_DMAR_TABLE) += dmar.o

obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o

obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o

drivers/iommu/amd_iommu.c

+73 −31
Original line number Diff line number Diff line
@@ -287,14 +287,27 @@ static struct pci_dev *get_isolation_root(struct pci_dev *pdev) 


	/*

	 * If it's a multifunction device that does not support our

	 * required ACS flags, add to the same group as function 0.

	 * required ACS flags, add to the same group as lowest numbered

	 * function that also does not suport the required ACS flags.

	 */

	if (dma_pdev->multifunction &&

	    !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))

		swap_pci_ref(&dma_pdev,

			     pci_get_slot(dma_pdev->bus,

					  PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),

					  0)));

	    !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {

		u8 i, slot = PCI_SLOT(dma_pdev->devfn);



		for (i = 0; i < 8; i++) {

			struct pci_dev *tmp;



			tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));

			if (!tmp)

				continue;



			if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {

				swap_pci_ref(&dma_pdev, tmp);

				break;

			}

			pci_dev_put(tmp);

		}

	}



	/*

	 * Devices on the root bus go through the iommu.  If that's not us,
@@ -1484,6 +1497,10 @@ static unsigned long iommu_unmap_page(struct protection_domain *dom, 


			/* Large PTE found which maps this address */

			unmap_size = PTE_PAGE_SIZE(*pte);



			/* Only unmap from the first pte in the page */

			if ((unmap_size - 1) & bus_addr)

				break;

			count      = PAGE_SIZE_PTE_COUNT(unmap_size);

			for (i = 0; i < count; i++)

				pte[i] = 0ULL;
@@ -1493,7 +1510,7 @@ static unsigned long iommu_unmap_page(struct protection_domain *dom, 
		unmapped += unmap_size;

	}



	BUG_ON(!is_power_of_2(unmapped));

	BUG_ON(unmapped && !is_power_of_2(unmapped));



	return unmapped;

}
@@ -1893,34 +1910,59 @@ static void domain_id_free(int id) 
	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);

}



#define DEFINE_FREE_PT_FN(LVL, FN)				\

static void free_pt_##LVL (unsigned long __pt)			\

{								\

	unsigned long p;					\

	u64 *pt;						\

	int i;							\

								\

	pt = (u64 *)__pt;					\

								\

	for (i = 0; i < 512; ++i) {				\

		if (!IOMMU_PTE_PRESENT(pt[i]))			\

			continue;				\

								\

		p = (unsigned long)IOMMU_PTE_PAGE(pt[i]);	\

		FN(p);						\

	}							\

	free_page((unsigned long)pt);				\

}



DEFINE_FREE_PT_FN(l2, free_page)

DEFINE_FREE_PT_FN(l3, free_pt_l2)

DEFINE_FREE_PT_FN(l4, free_pt_l3)

DEFINE_FREE_PT_FN(l5, free_pt_l4)

DEFINE_FREE_PT_FN(l6, free_pt_l5)



static void free_pagetable(struct protection_domain *domain)

{

	int i, j;

	u64 *p1, *p2, *p3;



	p1 = domain->pt_root;

	unsigned long root = (unsigned long)domain->pt_root;



	if (!p1)

		return;



	for (i = 0; i < 512; ++i) {

		if (!IOMMU_PTE_PRESENT(p1[i]))

			continue;



		p2 = IOMMU_PTE_PAGE(p1[i]);

		for (j = 0; j < 512; ++j) {

			if (!IOMMU_PTE_PRESENT(p2[j]))

				continue;

			p3 = IOMMU_PTE_PAGE(p2[j]);

			free_page((unsigned long)p3);

		}



		free_page((unsigned long)p2);

	switch (domain->mode) {

	case PAGE_MODE_NONE:

		break;

	case PAGE_MODE_1_LEVEL:

		free_page(root);

		break;

	case PAGE_MODE_2_LEVEL:

		free_pt_l2(root);

		break;

	case PAGE_MODE_3_LEVEL:

		free_pt_l3(root);

		break;

	case PAGE_MODE_4_LEVEL:

		free_pt_l4(root);

		break;

	case PAGE_MODE_5_LEVEL:

		free_pt_l5(root);

		break;

	case PAGE_MODE_6_LEVEL:

		free_pt_l6(root);

		break;

	default:

		BUG();

	}



	free_page((unsigned long)p1);



	domain->pt_root = NULL;

}



static void free_gcr3_tbl_level1(u64 *tbl)