MIPS: BMIPS: change compile time checks to runtime checks (6465460c) · Commits · e / devices / android_kernel_teracube_emerald

arch/mips/bcm63xx/prom.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -61,7 +61,7 @@ void __init prom_init(void)

	if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {		if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
	/* set up SMP */		/* set up SMP */
	register_smp_ops(&bmips_smp_ops);		register_smp_ops(&bmips43xx_smp_ops);

	/*		/*
	* BCM6328 might not have its second CPU enabled, while BCM3368		* BCM6328 might not have its second CPU enabled, while BCM3368

arch/mips/include/asm/bmips.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -47,7 +47,8 @@
	#include <linux/cpumask.h>		#include <linux/cpumask.h>
	#include <asm/r4kcache.h>		#include <asm/r4kcache.h>

	extern struct plat_smp_ops bmips_smp_ops;		extern struct plat_smp_ops bmips43xx_smp_ops;
			extern struct plat_smp_ops bmips5000_smp_ops;
	extern char bmips_reset_nmi_vec;		extern char bmips_reset_nmi_vec;
	extern char bmips_reset_nmi_vec_end;		extern char bmips_reset_nmi_vec_end;
	extern char bmips_smp_movevec;		extern char bmips_smp_movevec;

arch/mips/kernel/bmips_vec.S

+43 −12

Original line number	Original line	Diff line number	Diff line
	@@ -13,6 +13,7 @@
	#include <asm/asm.h>		#include <asm/asm.h>
	#include <asm/asmmacro.h>		#include <asm/asmmacro.h>
	#include <asm/cacheops.h>		#include <asm/cacheops.h>
			#include <asm/cpu.h>
	#include <asm/regdef.h>		#include <asm/regdef.h>
	#include <asm/mipsregs.h>		#include <asm/mipsregs.h>
	#include <asm/stackframe.h>		#include <asm/stackframe.h>
	@@ -91,12 +92,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
	beqz k0, bmips_smp_entry		beqz k0, bmips_smp_entry

	#if defined(CONFIG_CPU_BMIPS5000)		#if defined(CONFIG_CPU_BMIPS5000)
			mfc0 k0, CP0_PRID
			li k1, PRID_IMP_BMIPS5000
			andi k0, 0xff00
			bne k0, k1, 1f

	/* if we're not on core 0, this must be the SMP boot signal */		/* if we're not on core 0, this must be the SMP boot signal */
	li k1, (3 << 25)		li k1, (3 << 25)
	mfc0 k0, $22		mfc0 k0, $22
	and k0, k1		and k0, k1
	bnez k0, bmips_smp_entry		bnez k0, bmips_smp_entry
	#endif		1:
			#endif /* CONFIG_CPU_BMIPS5000 */
	#endif /* CONFIG_SMP */		#endif /* CONFIG_SMP */

	/* nope, it's just a regular NMI */		/* nope, it's just a regular NMI */
	@@ -139,7 +146,12 @@ bmips_smp_entry:
	xori k0, 0x04		xori k0, 0x04
	mtc0 k0, CP0_CONFIG		mtc0 k0, CP0_CONFIG

			mfc0 k0, CP0_PRID
			andi k0, 0xff00
	#if defined(CONFIG_CPU_BMIPS4350) \|\| defined(CONFIG_CPU_BMIPS4380)		#if defined(CONFIG_CPU_BMIPS4350) \|\| defined(CONFIG_CPU_BMIPS4380)
			li k1, PRID_IMP_BMIPS43XX
			bne k0, k1, 2f

	/* initialize CPU1's local I-cache */		/* initialize CPU1's local I-cache */
	li k0, 0x80000000		li k0, 0x80000000
	li k1, 0x80010000		li k1, 0x80010000
	@@ -150,14 +162,21 @@ bmips_smp_entry:
	1: cache Index_Store_Tag_I, 0(k0)		1: cache Index_Store_Tag_I, 0(k0)
	addiu k0, 16		addiu k0, 16
	bne k0, k1, 1b		bne k0, k1, 1b
	#elif defined(CONFIG_CPU_BMIPS5000)
			b 3f
			2:
			#endif /* CONFIG_CPU_BMIPS4350 \|\| CONFIG_CPU_BMIPS4380 */
			#if defined(CONFIG_CPU_BMIPS5000)
	/* set exception vector base */		/* set exception vector base */
			li k1, PRID_IMP_BMIPS5000
			bne k0, k1, 3f

	la k0, ebase		la k0, ebase
	lw k0, 0(k0)		lw k0, 0(k0)
	mtc0 k0, $15, 1		mtc0 k0, $15, 1
	BARRIER		BARRIER
	#endif		#endif /* CONFIG_CPU_BMIPS5000 */
			3:
	/* jump back to kseg0 in case we need to remap the kseg1 area */		/* jump back to kseg0 in case we need to remap the kseg1 area */
	la k0, 1f		la k0, 1f
	jr k0		jr k0
	@@ -221,8 +240,18 @@ END(bmips_smp_int_vec)
	LEAF(bmips_enable_xks01)		LEAF(bmips_enable_xks01)

	#if defined(CONFIG_XKS01)		#if defined(CONFIG_XKS01)
			mfc0 t0, CP0_PRID
			andi t2, t0, 0xff00
	#if defined(CONFIG_CPU_BMIPS4380)		#if defined(CONFIG_CPU_BMIPS4380)
			li t1, PRID_IMP_BMIPS43XX
			bne t2, t1, 1f

			andi t0, 0xff
			addiu t1, t0, -PRID_REV_BMIPS4380_HI
			bgtz t1, 2f
			addiu t0, -PRID_REV_BMIPS4380_LO
			bltz t0, 2f

	mfc0 t0, $22, 3		mfc0 t0, $22, 3
	li t1, 0x1ff0		li t1, 0x1ff0
	li t2, (1 << 12) \| (1 << 9)		li t2, (1 << 12) \| (1 << 9)
	@@ -231,7 +260,13 @@ LEAF(bmips_enable_xks01)
	or t0, t2		or t0, t2
	mtc0 t0, $22, 3		mtc0 t0, $22, 3
	BARRIER		BARRIER
	#elif defined(CONFIG_CPU_BMIPS5000)		b 2f
			1:
			#endif /* CONFIG_CPU_BMIPS4380 */
			#if defined(CONFIG_CPU_BMIPS5000)
			li t1, PRID_IMP_BMIPS5000
			bne t2, t1, 2f

	mfc0 t0, $22, 5		mfc0 t0, $22, 5
	li t1, 0x01ff		li t1, 0x01ff
	li t2, (1 << 8) \| (1 << 5)		li t2, (1 << 8) \| (1 << 5)
	@@ -240,12 +275,8 @@ LEAF(bmips_enable_xks01)
	or t0, t2		or t0, t2
	mtc0 t0, $22, 5		mtc0 t0, $22, 5
	BARRIER		BARRIER
	#else		#endif /* CONFIG_CPU_BMIPS5000 */
			2:
	#error Missing XKS01 setup

	#endif

	#endif /* defined(CONFIG_XKS01) */		#endif /* defined(CONFIG_XKS01) */

	jr ra		jr ra

arch/mips/kernel/smp-bmips.c

+189 −123

Original line number	Original line	Diff line number	Diff line
	@@ -49,8 +49,10 @@ cpumask_t bmips_booted_mask;
	unsigned long bmips_smp_boot_sp;		unsigned long bmips_smp_boot_sp;
	unsigned long bmips_smp_boot_gp;		unsigned long bmips_smp_boot_gp;

	static void bmips_send_ipi_single(int cpu, unsigned int action);		static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
	static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);		static void bmips5000_send_ipi_single(int cpu, unsigned int action);
			static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
			static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);

	/* SW interrupts 0,1 are used for interprocessor signaling */		/* SW interrupts 0,1 are used for interprocessor signaling */
	#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)		#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
	@@ -64,10 +66,11 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
	static void __init bmips_smp_setup(void)		static void __init bmips_smp_setup(void)
	{		{
	int i, cpu = 1, boot_cpu = 0;		int i, cpu = 1, boot_cpu = 0;

	#if defined(CONFIG_CPU_BMIPS4350) \|\| defined(CONFIG_CPU_BMIPS4380)
	int cpu_hw_intr;		int cpu_hw_intr;

			switch (current_cpu_type()) {
			case CPU_BMIPS4350:
			case CPU_BMIPS4380:
	/* arbitration priority */		/* arbitration priority */
	clear_c0_brcm_cmt_ctrl(0x30);		clear_c0_brcm_cmt_ctrl(0x30);

	@@ -78,7 +81,8 @@ static void __init bmips_smp_setup(void)
	boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));		boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));

	/*		/*
	* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread		* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
			* thread
	* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output		* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
	* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output		* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
	*/		*/
	@@ -87,11 +91,14 @@ static void __init bmips_smp_setup(void)
	else		else
	cpu_hw_intr = 0x1d;		cpu_hw_intr = 0x1d;

	change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) \| (0x03 << 15));		change_c0_brcm_cmt_intr(0xf8018000,
			(cpu_hw_intr << 27) \| (0x03 << 15));

	/* single core, 2 threads (2 pipelines) */		/* single core, 2 threads (2 pipelines) */
	max_cpus = 2;		max_cpus = 2;
	#elif defined(CONFIG_CPU_BMIPS5000)
			break;
			case CPU_BMIPS5000:
	/* enable raceless SW interrupts */		/* enable raceless SW interrupts */
	set_c0_brcm_config(0x03 << 22);		set_c0_brcm_config(0x03 << 22);

	@@ -106,7 +113,11 @@ static void __init bmips_smp_setup(void)
	write_c0_brcm_action(ACTION_CLR_IPI(i, 0));		write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
	write_c0_brcm_action(ACTION_CLR_IPI(i, 1));		write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
	}		}
	#endif
			break;
			default:
			max_cpus = 1;
			}

	if (!bmips_smp_enabled)		if (!bmips_smp_enabled)
	max_cpus = 1;		max_cpus = 1;
	@@ -134,6 +145,20 @@ static void __init bmips_smp_setup(void)
	*/		*/
	static void bmips_prepare_cpus(unsigned int max_cpus)		static void bmips_prepare_cpus(unsigned int max_cpus)
	{		{
			irqreturn_t (bmips_ipi_interrupt)(int irq, void dev_id);

			switch (current_cpu_type()) {
			case CPU_BMIPS4350:
			case CPU_BMIPS4380:
			bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
			break;
			case CPU_BMIPS5000:
			bmips_ipi_interrupt = bmips5000_ipi_interrupt;
			break;
			default:
			return;
			}

	if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,		if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
	"smp_ipi0", NULL))		"smp_ipi0", NULL))
	panic("Can't request IPI0 interrupt");		panic("Can't request IPI0 interrupt");
	@@ -168,14 +193,26 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)

	pr_info("SMP: Booting CPU%d...\n", cpu);		pr_info("SMP: Booting CPU%d...\n", cpu);

	if (cpumask_test_cpu(cpu, &bmips_booted_mask))		if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
	bmips_send_ipi_single(cpu, 0);		switch (current_cpu_type()) {
			case CPU_BMIPS4350:
			case CPU_BMIPS4380:
			bmips43xx_send_ipi_single(cpu, 0);
			break;
			case CPU_BMIPS5000:
			bmips5000_send_ipi_single(cpu, 0);
			break;
			}
			}
	else {		else {
	#if defined(CONFIG_CPU_BMIPS4350) \|\| defined(CONFIG_CPU_BMIPS4380)		switch (current_cpu_type()) {
			case CPU_BMIPS4350:
			case CPU_BMIPS4380:
	/* Reset slave TP1 if booting from TP0 */		/* Reset slave TP1 if booting from TP0 */
	if (cpu_logical_map(cpu) == 1)		if (cpu_logical_map(cpu) == 1)
	set_c0_brcm_cmt_ctrl(0x01);		set_c0_brcm_cmt_ctrl(0x01);
	#elif defined(CONFIG_CPU_BMIPS5000)		break;
			case CPU_BMIPS5000:
	if (cpu & 0x01)		if (cpu & 0x01)
	write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));		write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
	else {		else {
	@@ -187,7 +224,8 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
	udelay(10);		udelay(10);
	bmips_write_zscm_reg(0x210, 0x00);		bmips_write_zscm_reg(0x210, 0x00);
	}		}
	#endif		break;
			}
	cpumask_set_cpu(cpu, &bmips_booted_mask);		cpumask_set_cpu(cpu, &bmips_booted_mask);
	}		}
	}		}
	@@ -199,12 +237,16 @@ static void bmips_init_secondary(void)
	{		{
	/* move NMI vector to kseg0, in case XKS01 is enabled */		/* move NMI vector to kseg0, in case XKS01 is enabled */

	#if defined(CONFIG_CPU_BMIPS4350) \|\| defined(CONFIG_CPU_BMIPS4380)		void __iomem *cbr;
	void __iomem *cbr = BMIPS_GET_CBR();
	unsigned long old_vec;		unsigned long old_vec;
	unsigned long relo_vector;		unsigned long relo_vector;
	int boot_cpu;		int boot_cpu;

			switch (current_cpu_type()) {
			case CPU_BMIPS4350:
			case CPU_BMIPS4380:
			cbr = BMIPS_GET_CBR();

	boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));		boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
	relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :		relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
	BMIPS_RELO_VECTOR_CONTROL_1;		BMIPS_RELO_VECTOR_CONTROL_1;
	@@ -213,12 +255,14 @@ static void bmips_init_secondary(void)
	__raw_writel(old_vec & ~0x20000000, cbr + relo_vector);		__raw_writel(old_vec & ~0x20000000, cbr + relo_vector);

	clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);		clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
	#elif defined(CONFIG_CPU_BMIPS5000)		break;
			case CPU_BMIPS5000:
	write_c0_brcm_bootvec(read_c0_brcm_bootvec() &		write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
	(smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));		(smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));

	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));		write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
	#endif		break;
			}
	}		}

	/*		/*
	@@ -243,8 +287,6 @@ static void bmips_cpus_done(void)
	{		{
	}		}

	#if defined(CONFIG_CPU_BMIPS5000)

	/*		/*
	* BMIPS5000 raceless IPIs		* BMIPS5000 raceless IPIs
	*		*
	@@ -253,12 +295,12 @@ static void bmips_cpus_done(void)
	* IPI1 is used for SMP_CALL_FUNCTION		* IPI1 is used for SMP_CALL_FUNCTION
	*/		*/

	static void bmips_send_ipi_single(int cpu, unsigned int action)		static void bmips5000_send_ipi_single(int cpu, unsigned int action)
	{		{
	write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));		write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
	}		}

	static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)		static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
	{		{
	int action = irq - IPI0_IRQ;		int action = irq - IPI0_IRQ;

	@@ -272,7 +314,14 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}

	#else		static void bmips5000_send_ipi_mask(const struct cpumask *mask,
			unsigned int action)
			{
			unsigned int i;

			for_each_cpu(i, mask)
			bmips5000_send_ipi_single(i, action);
			}

	/*		/*
	* BMIPS43xx racey IPIs		* BMIPS43xx racey IPIs
	@@ -287,7 +336,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
	static DEFINE_SPINLOCK(ipi_lock);		static DEFINE_SPINLOCK(ipi_lock);
	static DEFINE_PER_CPU(int, ipi_action_mask);		static DEFINE_PER_CPU(int, ipi_action_mask);

	static void bmips_send_ipi_single(int cpu, unsigned int action)		static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
	{		{
	unsigned long flags;		unsigned long flags;

	@@ -298,7 +347,7 @@ static void bmips_send_ipi_single(int cpu, unsigned int action)
	spin_unlock_irqrestore(&ipi_lock, flags);		spin_unlock_irqrestore(&ipi_lock, flags);
	}		}

	static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)		static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
	{		{
	unsigned long flags;		unsigned long flags;
	int action, cpu = irq - IPI0_IRQ;		int action, cpu = irq - IPI0_IRQ;
	@@ -317,15 +366,13 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}

	#endif /* BMIPS type */		static void bmips43xx_send_ipi_mask(const struct cpumask *mask,

	static void bmips_send_ipi_mask(const struct cpumask *mask,
	unsigned int action)		unsigned int action)
	{		{
	unsigned int i;		unsigned int i;

	for_each_cpu(i, mask)		for_each_cpu(i, mask)
	bmips_send_ipi_single(i, action);		bmips43xx_send_ipi_single(i, action);
	}		}

	#ifdef CONFIG_HOTPLUG_CPU		#ifdef CONFIG_HOTPLUG_CPU
	@@ -381,15 +428,30 @@ void __ref play_dead(void)

	#endif /* CONFIG_HOTPLUG_CPU */		#endif /* CONFIG_HOTPLUG_CPU */

	struct plat_smp_ops bmips_smp_ops = {		struct plat_smp_ops bmips43xx_smp_ops = {
			.smp_setup = bmips_smp_setup,
			.prepare_cpus = bmips_prepare_cpus,
			.boot_secondary = bmips_boot_secondary,
			.smp_finish = bmips_smp_finish,
			.init_secondary = bmips_init_secondary,
			.cpus_done = bmips_cpus_done,
			.send_ipi_single = bmips43xx_send_ipi_single,
			.send_ipi_mask = bmips43xx_send_ipi_mask,
			#ifdef CONFIG_HOTPLUG_CPU
			.cpu_disable = bmips_cpu_disable,
			.cpu_die = bmips_cpu_die,
			#endif
			};

			struct plat_smp_ops bmips5000_smp_ops = {
	.smp_setup = bmips_smp_setup,		.smp_setup = bmips_smp_setup,
	.prepare_cpus = bmips_prepare_cpus,		.prepare_cpus = bmips_prepare_cpus,
	.boot_secondary = bmips_boot_secondary,		.boot_secondary = bmips_boot_secondary,
	.smp_finish = bmips_smp_finish,		.smp_finish = bmips_smp_finish,
	.init_secondary = bmips_init_secondary,		.init_secondary = bmips_init_secondary,
	.cpus_done = bmips_cpus_done,		.cpus_done = bmips_cpus_done,
	.send_ipi_single = bmips_send_ipi_single,		.send_ipi_single = bmips5000_send_ipi_single,
	.send_ipi_mask = bmips_send_ipi_mask,		.send_ipi_mask = bmips5000_send_ipi_mask,
	#ifdef CONFIG_HOTPLUG_CPU		#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable = bmips_cpu_disable,		.cpu_disable = bmips_cpu_disable,
	.cpu_die = bmips_cpu_die,		.cpu_die = bmips_cpu_die,
	@@ -427,7 +489,8 @@ void bmips_ebase_setup(void)

	BUG_ON(ebase != CKSEG0);		BUG_ON(ebase != CKSEG0);

	#if defined(CONFIG_CPU_BMIPS4350)		switch (current_cpu_type()) {
			case CPU_BMIPS4350:
	/*		/*
	* BMIPS4350 cannot relocate the normal vectors, but it		* BMIPS4350 cannot relocate the normal vectors, but it
	* can relocate the BEV=1 vectors. So CPU1 starts up at		* can relocate the BEV=1 vectors. So CPU1 starts up at
	@@ -442,7 +505,7 @@ void bmips_ebase_setup(void)
	&bmips_smp_int_vec, 0x80);		&bmips_smp_int_vec, 0x80);
	__sync();		__sync();
	return;		return;
	#elif defined(CONFIG_CPU_BMIPS4380)		case CPU_BMIPS4380:
	/*		/*
	* 0x8000_0000: reset/NMI (initially in kseg1)		* 0x8000_0000: reset/NMI (initially in kseg1)
	* 0x8000_0400: normal vectors		* 0x8000_0400: normal vectors
	@@ -451,7 +514,8 @@ void bmips_ebase_setup(void)
	cbr = BMIPS_GET_CBR();		cbr = BMIPS_GET_CBR();
	__raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);		__raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
	__raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);		__raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
	#elif defined(CONFIG_CPU_BMIPS5000)		break;
			case CPU_BMIPS5000:
	/*		/*
	* 0x8000_0000: reset/NMI (initially in kseg1)		* 0x8000_0000: reset/NMI (initially in kseg1)
	* 0x8000_1000: normal vectors		* 0x8000_1000: normal vectors
	@@ -461,9 +525,11 @@ void bmips_ebase_setup(void)
	write_c0_ebase(new_ebase);		write_c0_ebase(new_ebase);
	if (max_cpus > 2)		if (max_cpus > 2)
	bmips_write_zscm_reg(0xa0, 0xa008a008);		bmips_write_zscm_reg(0xa0, 0xa008a008);
	#else		break;
			default:
	return;		return;
	#endif		}

	board_nmi_handler_setup = &bmips_nmi_handler_setup;		board_nmi_handler_setup = &bmips_nmi_handler_setup;
	ebase = new_ebase;		ebase = new_ebase;
	}		}