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Commit 63c3a66f authored by Joe Perches's avatar Joe Perches Committed by David S. Miller
Browse files

tg3: Convert u32 flag,flg2,flg3 uses to bitmap 



Using a bitmap instead of separate u32 flags allows a consistent, simpler
and more extensible mechanism to determine capabilities.

Convert bitmasks to enum.
Add tg3_flag, tg3_flag_clear and tg3_flag_set.
Convert the flag & bitmask tests.

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Acked-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fa2bd7ff

drivers/net/tg3.c

+645 −654

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/tg3.h

+83 −85
Original line number Diff line number Diff line
@@ -2816,6 +2816,86 @@ struct tg3_napi { 
	unsigned int			irq_vec;

};



enum TG3_FLAGS {

	TG3_FLAG_TAGGED_STATUS = 0,

	TG3_FLAG_TXD_MBOX_HWBUG,

	TG3_FLAG_USE_LINKCHG_REG,

	TG3_FLAG_ERROR_PROCESSED,

	TG3_FLAG_ENABLE_ASF,

	TG3_FLAG_ASPM_WORKAROUND,

	TG3_FLAG_POLL_SERDES,

	TG3_FLAG_MBOX_WRITE_REORDER,

	TG3_FLAG_PCIX_TARGET_HWBUG,

	TG3_FLAG_WOL_SPEED_100MB,

	TG3_FLAG_WOL_ENABLE,

	TG3_FLAG_EEPROM_WRITE_PROT,

	TG3_FLAG_NVRAM,

	TG3_FLAG_NVRAM_BUFFERED,

	TG3_FLAG_SUPPORT_MSI,

	TG3_FLAG_SUPPORT_MSIX,

	TG3_FLAG_PCIX_MODE,

	TG3_FLAG_PCI_HIGH_SPEED,

	TG3_FLAG_PCI_32BIT,

	TG3_FLAG_SRAM_USE_CONFIG,

	TG3_FLAG_TX_RECOVERY_PENDING,

	TG3_FLAG_WOL_CAP,

	TG3_FLAG_JUMBO_RING_ENABLE,

	TG3_FLAG_PAUSE_AUTONEG,

	TG3_FLAG_CPMU_PRESENT,

	TG3_FLAG_40BIT_DMA_BUG,

	TG3_FLAG_BROKEN_CHECKSUMS,

	TG3_FLAG_JUMBO_CAPABLE,

	TG3_FLAG_CHIP_RESETTING,

	TG3_FLAG_INIT_COMPLETE,

	TG3_FLAG_RESTART_TIMER,

	TG3_FLAG_TSO_BUG,

	TG3_FLAG_IS_5788,

	TG3_FLAG_MAX_RXPEND_64,

	TG3_FLAG_TSO_CAPABLE,

	TG3_FLAG_PCI_EXPRESS,

	TG3_FLAG_ASF_NEW_HANDSHAKE,

	TG3_FLAG_HW_AUTONEG,

	TG3_FLAG_IS_NIC,

	TG3_FLAG_FLASH,

	TG3_FLAG_HW_TSO_1,

	TG3_FLAG_5705_PLUS,

	TG3_FLAG_5750_PLUS,

	TG3_FLAG_HW_TSO_3,

	TG3_FLAG_USING_MSI,

	TG3_FLAG_USING_MSIX,

	TG3_FLAG_ICH_WORKAROUND,

	TG3_FLAG_5780_CLASS,

	TG3_FLAG_HW_TSO_2,

	TG3_FLAG_1SHOT_MSI,

	TG3_FLAG_NO_FWARE_REPORTED,

	TG3_FLAG_NO_NVRAM_ADDR_TRANS,

	TG3_FLAG_ENABLE_APE,

	TG3_FLAG_PROTECTED_NVRAM,

	TG3_FLAG_5701_DMA_BUG,

	TG3_FLAG_USE_PHYLIB,

	TG3_FLAG_MDIOBUS_INITED,

	TG3_FLAG_LRG_PROD_RING_CAP,

	TG3_FLAG_RGMII_INBAND_DISABLE,

	TG3_FLAG_RGMII_EXT_IBND_RX_EN,

	TG3_FLAG_RGMII_EXT_IBND_TX_EN,

	TG3_FLAG_CLKREQ_BUG,

	TG3_FLAG_5755_PLUS,

	TG3_FLAG_NO_NVRAM,

	TG3_FLAG_ENABLE_RSS,

	TG3_FLAG_ENABLE_TSS,

	TG3_FLAG_4G_DMA_BNDRY_BUG,

	TG3_FLAG_40BIT_DMA_LIMIT_BUG,

	TG3_FLAG_SHORT_DMA_BUG,

	TG3_FLAG_USE_JUMBO_BDFLAG,

	TG3_FLAG_L1PLLPD_EN,

	TG3_FLAG_57765_PLUS,

	TG3_FLAG_APE_HAS_NCSI,

	TG3_FLAG_5717_PLUS,



	/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */

	TG3_FLAG_NUMBER_OF_FLAGS,	/* Last entry in enum TG3_FLAGS */

};



struct tg3 {

	/* begin "general, frequently-used members" cacheline section */
@@ -2839,7 +2919,7 @@ struct tg3 { 
	/* SMP locking strategy:

	 *

	 * lock: Held during reset, PHY access, timer, and when

	 *       updating tg3_flags and tg3_flags2.

	 *       updating tg3_flags.

	 *

	 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds

	 *                netif_tx_lock when it needs to call
@@ -2896,95 +2976,13 @@ struct tg3 { 
	struct tg3_ethtool_stats	estats;

	struct tg3_ethtool_stats	estats_prev;



	DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);



	union {

	unsigned long			phy_crc_errors;

	unsigned long			last_event_jiffies;

	};



	u32				tg3_flags;

#define TG3_FLAG_TAGGED_STATUS		0x00000001

#define TG3_FLAG_TXD_MBOX_HWBUG		0x00000002

#define TG3_FLAG_USE_LINKCHG_REG	0x00000008

#define TG3_FLAG_ERROR_PROCESSED	0x00000010

#define TG3_FLAG_ENABLE_ASF		0x00000020

#define TG3_FLAG_ASPM_WORKAROUND	0x00000040

#define TG3_FLAG_POLL_SERDES		0x00000080

#define TG3_FLAG_MBOX_WRITE_REORDER	0x00000100

#define TG3_FLAG_PCIX_TARGET_HWBUG	0x00000200

#define TG3_FLAG_WOL_SPEED_100MB	0x00000400

#define TG3_FLAG_WOL_ENABLE		0x00000800

#define TG3_FLAG_EEPROM_WRITE_PROT	0x00001000

#define TG3_FLAG_NVRAM			0x00002000

#define TG3_FLAG_NVRAM_BUFFERED		0x00004000

#define TG3_FLAG_SUPPORT_MSI		0x00008000

#define TG3_FLAG_SUPPORT_MSIX		0x00010000

#define TG3_FLAG_SUPPORT_MSI_OR_MSIX	(TG3_FLAG_SUPPORT_MSI | \

					 TG3_FLAG_SUPPORT_MSIX)

#define TG3_FLAG_PCIX_MODE		0x00020000

#define TG3_FLAG_PCI_HIGH_SPEED		0x00040000

#define TG3_FLAG_PCI_32BIT		0x00080000

#define TG3_FLAG_SRAM_USE_CONFIG	0x00100000

#define TG3_FLAG_TX_RECOVERY_PENDING	0x00200000

#define TG3_FLAG_WOL_CAP		0x00400000

#define TG3_FLAG_JUMBO_RING_ENABLE	0x00800000

#define TG3_FLAG_PAUSE_AUTONEG		0x02000000

#define TG3_FLAG_CPMU_PRESENT		0x04000000

#define TG3_FLAG_40BIT_DMA_BUG		0x08000000

#define TG3_FLAG_JUMBO_CAPABLE		0x20000000

#define TG3_FLAG_CHIP_RESETTING		0x40000000

#define TG3_FLAG_INIT_COMPLETE		0x80000000

	u32				tg3_flags2;

#define TG3_FLG2_RESTART_TIMER		0x00000001

#define TG3_FLG2_TSO_BUG		0x00000002

#define TG3_FLG2_IS_5788		0x00000008

#define TG3_FLG2_MAX_RXPEND_64		0x00000010

#define TG3_FLG2_TSO_CAPABLE		0x00000020

#define TG3_FLG2_PCI_EXPRESS		0x00000200

#define TG3_FLG2_ASF_NEW_HANDSHAKE	0x00000400

#define TG3_FLG2_HW_AUTONEG		0x00000800

#define TG3_FLG2_IS_NIC			0x00001000

#define TG3_FLG2_FLASH			0x00008000

#define TG3_FLG2_HW_TSO_1		0x00010000

#define TG3_FLG2_5705_PLUS		0x00040000

#define TG3_FLG2_5750_PLUS		0x00080000

#define TG3_FLG2_HW_TSO_3		0x00100000

#define TG3_FLG2_USING_MSI		0x00200000

#define TG3_FLG2_USING_MSIX		0x00400000

#define TG3_FLG2_USING_MSI_OR_MSIX	(TG3_FLG2_USING_MSI | \

					TG3_FLG2_USING_MSIX)

#define TG3_FLG2_ICH_WORKAROUND		0x02000000

#define TG3_FLG2_5780_CLASS		0x04000000

#define TG3_FLG2_HW_TSO_2		0x08000000

#define TG3_FLG2_HW_TSO			(TG3_FLG2_HW_TSO_1 | \

					 TG3_FLG2_HW_TSO_2 | \

					 TG3_FLG2_HW_TSO_3)

#define TG3_FLG2_1SHOT_MSI		0x10000000

#define TG3_FLG2_NO_FWARE_REPORTED	0x40000000

	u32				tg3_flags3;

#define TG3_FLG3_NO_NVRAM_ADDR_TRANS	0x00000001

#define TG3_FLG3_ENABLE_APE		0x00000002

#define TG3_FLG3_PROTECTED_NVRAM	0x00000004

#define TG3_FLG3_5701_DMA_BUG		0x00000008

#define TG3_FLG3_USE_PHYLIB		0x00000010

#define TG3_FLG3_MDIOBUS_INITED		0x00000020

#define TG3_FLG3_LRG_PROD_RING_CAP	0x00000080

#define TG3_FLG3_RGMII_INBAND_DISABLE	0x00000100

#define TG3_FLG3_RGMII_EXT_IBND_RX_EN	0x00000200

#define TG3_FLG3_RGMII_EXT_IBND_TX_EN	0x00000400

#define TG3_FLG3_CLKREQ_BUG		0x00000800

#define TG3_FLG3_5755_PLUS		0x00002000

#define TG3_FLG3_NO_NVRAM		0x00004000

#define TG3_FLG3_ENABLE_RSS		0x00020000

#define TG3_FLG3_ENABLE_TSS		0x00040000

#define TG3_FLG3_4G_DMA_BNDRY_BUG	0x00080000

#define TG3_FLG3_40BIT_DMA_LIMIT_BUG	0x00100000

#define TG3_FLG3_SHORT_DMA_BUG		0x00200000

#define TG3_FLG3_USE_JUMBO_BDFLAG	0x00400000

#define TG3_FLG3_L1PLLPD_EN		0x00800000

#define TG3_FLG3_57765_PLUS		0x01000000

#define TG3_FLG3_APE_HAS_NCSI		0x02000000

#define TG3_FLG3_5717_PLUS		0x04000000



	struct timer_list		timer;

	u16				timer_counter;

	u16				timer_multiplier;