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Commit 62f0a11e authored by Chris Wilson's avatar Chris Wilson Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Fix relocation of shadow bb 



set_gma_to_bb_cmd() is completely bogus - it is (incorrectly) applying
the rules to read a GTT offset from a command as opposed to writing the
GTT offset. And to cap it all set_gma_to_bb_cmd() is called within a list
iterator of the most strange construction.

Fixes: be1da707 ("drm/i915/gvt: vGPU command scanner")
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Yulei Zhang <yulei.zhang@intel.com>
Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.10-rc1+
Tested-by: default avatarTina Zhang <tina.zhang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 58c744da

drivers/gpu/drm/i915/gvt/execlist.c

+18 −46
Original line number Diff line number Diff line
@@ -364,43 +364,16 @@ static void free_workload(struct intel_vgpu_workload *workload) 
#define get_desc_from_elsp_dwords(ed, i) \

	((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))





#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))

#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))

static int set_gma_to_bb_cmd(struct intel_shadow_bb_entry *entry_obj,

			     unsigned long add, int gmadr_bytes)

{

	if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))

		return -1;



	*((u32 *)(entry_obj->bb_start_cmd_va + (1 << 2))) = add &

		BATCH_BUFFER_ADDR_MASK;

	if (gmadr_bytes == 8) {

		*((u32 *)(entry_obj->bb_start_cmd_va + (2 << 2))) =

			add & BATCH_BUFFER_ADDR_HIGH_MASK;

	}



	return 0;

}



static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)

{

	int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;

	const int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;

	struct intel_shadow_bb_entry *entry_obj;



	/* pin the gem object to ggtt */

	if (!list_empty(&workload->shadow_bb)) {

		struct intel_shadow_bb_entry *entry_obj =

			list_first_entry(&workload->shadow_bb,

					 struct intel_shadow_bb_entry,

					 list);

		struct intel_shadow_bb_entry *temp;



		list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,

				list) {

	list_for_each_entry(entry_obj, &workload->shadow_bb, list) {

		struct i915_vma *vma;



			vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0,

						       4, 0);

		vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);

		if (IS_ERR(vma)) {

			gvt_err("Cannot pin\n");

			return;
@@ -412,10 +385,9 @@ static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 
		 */



		/* update the relocate gma with shadow batch buffer*/

			set_gma_to_bb_cmd(entry_obj,

					  i915_ggtt_offset(vma),

					  gmadr_bytes);

		}

		entry_obj->bb_start_cmd_va[1] = i915_ggtt_offset(vma);

		if (gmadr_bytes == 8)

			entry_obj->bb_start_cmd_va[2] = 0;

	}

}

drivers/gpu/drm/i915/gvt/scheduler.h

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ struct intel_shadow_bb_entry { 
	struct drm_i915_gem_object *obj;

	void *va;

	unsigned long len;

	void *bb_start_cmd_va;

	u32 *bb_start_cmd_va;

};



#define workload_q_head(vgpu, ring_id) \