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Commit 623aab89 authored by Cyrill Gorcunov's avatar Cyrill Gorcunov Committed by Ingo Molnar
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perf, x86: P4 PMU -- do a real check for ESCR address being in hash 



To prevent from clashes in future code modifications
do a real check for ESCR address being in hash. At
moment the callers are known to pass sane values but
better to be on a safe side.

And comment fix.

Signed-off-by: default avatarCyrill Gorcunov <gorcunov@openvz.org>
CC: Lin Ming <ming.m.lin@intel.com>
CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
CC: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100518212439.004503600@openvz.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 151f85a4

arch/x86/kernel/cpu/perf_event_p4.c

+4 −3
Original line number Diff line number Diff line
@@ -670,7 +670,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu) 


/*

 * ESCR address hashing is tricky, ESCRs are not sequential

 * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03e0) and

 * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and

 * the metric between any ESCRs is laid in range [0xa0,0xe1]

 *

 * so we make ~70% filled hashtable
@@ -736,7 +736,8 @@ static int p4_get_escr_idx(unsigned int addr) 
	unsigned int idx = P4_ESCR_MSR_IDX(addr);



	if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE	||

			!p4_escr_table[idx])) {

			!p4_escr_table[idx]		||

			p4_escr_table[idx] != addr)) {

		WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);

		return -1;

	}