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Commit 62310e51 authored by Bryan Wu's avatar Bryan Wu Committed by Linus Torvalds
Browse files

spi: spi_bfin: update handling of delay-after-deselect 

Move cs_chg_udelay handling (specific to this driver) to cs_deactive(), fixing
a bug when some SPI LCD driver needs delay after cs_deactive.

Fix bug reported by Cameron Barfield <cbarfield@cyberdata.net>
https://blackfin.uclinux.org/gf/project/uclinux-dist/forum/?action=ForumBrowse&forum_id=39&_forum_action=ForumMessageBrowse&thread_id=23630&feedback=Message%20replied

.

Cc: Cameron Barfield <cbarfield@cyberdata.net>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent c3061abb

drivers/spi/spi_bfin5xx.c

+9 −15
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ struct chip_data { 
	u8 enable_dma;

	u8 bits_per_word;	/* 8 or 16 */

	u8 cs_change_per_word;

	u8 cs_chg_udelay;

	u16 cs_chg_udelay;	/* Some devices require > 255usec delay */

	void (*write) (struct driver_data *);

	void (*read) (struct driver_data *);

	void (*duplex) (struct driver_data *);
@@ -211,6 +211,10 @@ static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip) 
	flag |= (chip->flag << 8);



	write_FLAG(drv_data, flag);



	/* Move delay here for consistency */

	if (chip->cs_chg_udelay)

		udelay(chip->cs_chg_udelay);

}



#define MAX_SPI_SSEL	7
@@ -307,10 +311,9 @@ static void u8_cs_chg_writer(struct driver_data *drv_data) 
		write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));

		while (read_STAT(drv_data) & BIT_STAT_TXS)

			continue;



		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);

		++drv_data->tx;

	}

}
@@ -359,9 +362,6 @@ static void u8_cs_chg_reader(struct driver_data *drv_data) 
	while (drv_data->rx < drv_data->rx_end - 1) {

		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);



		while (!(read_STAT(drv_data) & BIT_STAT_RXS))

			continue;

		cs_active(drv_data, chip);
@@ -412,10 +412,9 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data) 
		while (!(read_STAT(drv_data) & BIT_STAT_RXS))

			continue;

		*(u8 *) (drv_data->rx) = read_RDBR(drv_data);



		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);

		++drv_data->rx;

		++drv_data->tx;

	}
@@ -452,10 +451,9 @@ static void u16_cs_chg_writer(struct driver_data *drv_data) 
		write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));

		while ((read_STAT(drv_data) & BIT_STAT_TXS))

			continue;



		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);

		drv_data->tx += 2;

	}

}
@@ -504,9 +502,6 @@ static void u16_cs_chg_reader(struct driver_data *drv_data) 
	while (drv_data->rx < drv_data->rx_end - 2) {

		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);



		while (!(read_STAT(drv_data) & BIT_STAT_RXS))

			continue;

		cs_active(drv_data, chip);
@@ -557,10 +552,9 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data) 
		while (!(read_STAT(drv_data) & BIT_STAT_RXS))

			continue;

		*(u16 *) (drv_data->rx) = read_RDBR(drv_data);



		cs_deactive(drv_data, chip);



		if (chip->cs_chg_udelay)

			udelay(chip->cs_chg_udelay);

		drv_data->rx += 2;

		drv_data->tx += 2;

	}

include/asm-blackfin/bfin5xx_spi.h

+1 −1
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ struct bfin5xx_spi_chip { 
	u8 enable_dma;

	u8 bits_per_word;

	u8 cs_change_per_word;

	u8 cs_chg_udelay;

	u16 cs_chg_udelay; /* Some devices require 16-bit delays */

};



#endif /* _SPI_CHANNEL_H_ */