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Commit 60f000a4 authored by Carolyn Wyborny's avatar Carolyn Wyborny Committed by Jeff Kirsher
Browse files

i40e: Add FEC for 25g 



This patch adds adminq support for Forward Error
Correction ("FEC")for 25g products.

Change-ID: Iaff4910737c239d2c730e5c22a313ce9c37d3964
Signed-off-by: default avatarCarolyn Wyborny <carolyn.wyborny@intel.com>
Signed-off-by: default avatarMitch Williams <mitch.a.williams@intel.com>
Signed-off-by: default avatarJacek Naczyk <jacek.naczyk@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 3123237a

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

+23 −2
Original line number Diff line number Diff line
@@ -1686,6 +1686,8 @@ struct i40e_aq_get_phy_abilities_resp { 
#define I40E_AQ_PHY_LINK_ENABLED	0x08

#define I40E_AQ_PHY_AN_ENABLED		0x10

#define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20

#define I40E_AQ_PHY_FEC_ABILITY_KR	0x40

#define I40E_AQ_PHY_FEC_ABILITY_RS	0x80

	__le16	eee_capability;

#define I40E_AQ_EEE_100BASE_TX		0x0002

#define I40E_AQ_EEE_1000BASE_T		0x0004
@@ -1701,7 +1703,16 @@ struct i40e_aq_get_phy_abilities_resp { 
#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02

#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04

#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08

	u8	mod_type_ext;

	u8	fec_cfg_curr_mod_ext_info;

#define I40E_AQ_ENABLE_FEC_KR		0x01

#define I40E_AQ_ENABLE_FEC_RS		0x02

#define I40E_AQ_REQUEST_FEC_KR		0x04

#define I40E_AQ_REQUEST_FEC_RS		0x08

#define I40E_AQ_ENABLE_FEC_AUTO		0x10

#define I40E_AQ_FEC

#define I40E_AQ_MODULE_TYPE_EXT_MASK	0xE0

#define I40E_AQ_MODULE_TYPE_EXT_SHIFT	5



	u8	ext_comp_code;

	u8	phy_id[4];

	u8	module_type[3];
@@ -1729,7 +1740,15 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */ 
#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02

#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04

#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08

	u8	reserved[2];

	u8	fec_config;

#define I40E_AQ_SET_FEC_ABILITY_KR	BIT(0)

#define I40E_AQ_SET_FEC_ABILITY_RS	BIT(1)

#define I40E_AQ_SET_FEC_REQUEST_KR	BIT(2)

#define I40E_AQ_SET_FEC_REQUEST_RS	BIT(3)

#define I40E_AQ_SET_FEC_AUTO		BIT(4)

#define I40E_AQ_PHY_FEC_CONFIG_SHIFT	0x0

#define I40E_AQ_PHY_FEC_CONFIG_MASK	(0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)

	u8	reserved;

};



I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
@@ -1819,6 +1838,8 @@ struct i40e_aqc_get_link_status { 
	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */

	__le16	max_frame_size;

	u8	config;

#define I40E_AQ_CONFIG_FEC_KR_ENA	0x01

#define I40E_AQ_CONFIG_FEC_RS_ENA	0x02

#define I40E_AQ_CONFIG_CRC_ENA		0x04

#define I40E_AQ_CONFIG_PACING_MASK	0x78

	u8	external_power_ability;

drivers/net/ethernet/intel/i40e/i40e_common.c

+2 −0
Original line number Diff line number Diff line
@@ -1714,6 +1714,8 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 
		config.eee_capability = abilities.eee_capability;

		config.eeer = abilities.eeer_val;

		config.low_power_ctrl = abilities.d3_lpan;

		config.fec_config = abilities.fec_cfg_curr_mod_ext_info &

				    I40E_AQ_PHY_FEC_CONFIG_MASK;

		status = i40e_aq_set_phy_config(hw, &config, NULL);



		if (status)

drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h

+23 −2
Original line number Diff line number Diff line
@@ -1683,6 +1683,8 @@ struct i40e_aq_get_phy_abilities_resp { 
#define I40E_AQ_PHY_LINK_ENABLED	0x08

#define I40E_AQ_PHY_AN_ENABLED		0x10

#define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20

#define I40E_AQ_PHY_FEC_ABILITY_KR	0x40

#define I40E_AQ_PHY_FEC_ABILITY_RS	0x80

	__le16	eee_capability;

#define I40E_AQ_EEE_100BASE_TX		0x0002

#define I40E_AQ_EEE_1000BASE_T		0x0004
@@ -1698,7 +1700,16 @@ struct i40e_aq_get_phy_abilities_resp { 
#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02

#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04

#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08

	u8	mod_type_ext;

	u8	fec_cfg_curr_mod_ext_info;

#define I40E_AQ_ENABLE_FEC_KR		0x01

#define I40E_AQ_ENABLE_FEC_RS		0x02

#define I40E_AQ_REQUEST_FEC_KR		0x04

#define I40E_AQ_REQUEST_FEC_RS		0x08

#define I40E_AQ_ENABLE_FEC_AUTO		0x10

#define I40E_AQ_FEC

#define I40E_AQ_MODULE_TYPE_EXT_MASK	0xE0

#define I40E_AQ_MODULE_TYPE_EXT_SHIFT	5



	u8	ext_comp_code;

	u8	phy_id[4];

	u8	module_type[3];
@@ -1726,7 +1737,15 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */ 
#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02

#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04

#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08

	u8	reserved[2];

	u8	fec_config;

#define I40E_AQ_SET_FEC_ABILITY_KR	BIT(0)

#define I40E_AQ_SET_FEC_ABILITY_RS	BIT(1)

#define I40E_AQ_SET_FEC_REQUEST_KR	BIT(2)

#define I40E_AQ_SET_FEC_REQUEST_RS	BIT(3)

#define I40E_AQ_SET_FEC_AUTO		BIT(4)

#define I40E_AQ_PHY_FEC_CONFIG_SHIFT	0x0

#define I40E_AQ_PHY_FEC_CONFIG_MASK	(0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)

	u8	reserved;

};



I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
@@ -1816,6 +1835,8 @@ struct i40e_aqc_get_link_status { 
	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */

	__le16	max_frame_size;

	u8	config;

#define I40E_AQ_CONFIG_FEC_KR_ENA	0x01

#define I40E_AQ_CONFIG_FEC_RS_ENA	0x02

#define I40E_AQ_CONFIG_CRC_ENA		0x04

#define I40E_AQ_CONFIG_PACING_MASK	0x78

	u8	external_power_ability;