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Commit 5fb23e35 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Greg Kroah-Hartman
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dmaengine: dw: override LLP support if asked in platform data 



There are at least two known devices, e.g. DMA controller found on ARC AXS101
SDP board, that have LLP register and no multi block transfer support at the
same time.

Override autodetection by user provided data.

Reported-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: default avatarBryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c072e113

drivers/dma/dw/core.c

+1 −5
Original line number Diff line number Diff line
@@ -1571,11 +1571,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) 
				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;

		} else {

			dwc->block_size = pdata->block_size;



			/* Check if channel supports multi block transfer */

			channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));

			dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;

			channel_writel(dwc, LLP, 0);

			dwc->nollp = pdata->is_nollp;

		}

	}

include/linux/platform_data/dma-dw.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ struct dw_dma_slave { 
 * @is_private: The device channels should be marked as private and not for

 *	by the general purpose DMA channel allocator.

 * @is_memcpy: The device channels do support memory-to-memory transfers.

 * @is_nollp: The device channels does not support multi block transfers.

 * @chan_allocation_order: Allocate channels starting from 0 or 7

 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.

 * @block_size: Maximum block size supported by the controller
@@ -51,6 +52,7 @@ struct dw_dma_platform_data { 
	unsigned int	nr_channels;

	bool		is_private;

	bool		is_memcpy;

	bool		is_nollp;

#define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */

#define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */

	unsigned char	chan_allocation_order;