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Commit 5f7c6907 authored by Kumar Gala's avatar Kumar Gala Committed by Paul Mackerras
Browse files

[PATCH] powerpc: Merged ppc_asm.h 



Merged ppc_asm.h between ppc32 & ppc64.  The majority of the file is
common between the two architectures excluding how a single GPR is
saved/restored and which GPRs are non-volatile.

Additionally, moved the ASM_CONST macro used on ppc64 into ppc_asm.h.

Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 0a1e1222

arch/ppc/kernel/head.S

+3 −3
Original line number Diff line number Diff line
@@ -804,7 +804,7 @@ load_up_altivec: 
	beq	1f

	add	r4,r4,r6

	addi	r4,r4,THREAD	/* want THREAD of last_task_used_altivec */

	SAVE_32VR(0,r10,r4)

	SAVE_32VRS(0,r10,r4)

	mfvscr	vr0

	li	r10,THREAD_VSCR

	stvx	vr0,r10,r4
@@ -824,7 +824,7 @@ load_up_altivec: 
	stw	r4,THREAD_USED_VR(r5)

	lvx	vr0,r10,r5

	mtvscr	vr0

	REST_32VR(0,r10,r5)

	REST_32VRS(0,r10,r5)

#ifndef CONFIG_SMP

	subi	r4,r5,THREAD

	sub	r4,r4,r6
@@ -870,7 +870,7 @@ giveup_altivec: 
	addi	r3,r3,THREAD		/* want THREAD of task */

	lwz	r5,PT_REGS(r3)

	cmpwi	0,r5,0

	SAVE_32VR(0, r4, r3)

	SAVE_32VRS(0, r4, r3)

	mfvscr	vr0

	li	r4,THREAD_VSCR

	stvx	vr0,r4,r3

arch/ppc/kernel/head_fsl_booke.S

+3 −3
Original line number Diff line number Diff line
@@ -853,7 +853,7 @@ load_up_spe: 
	cmpi	0,r4,0

	beq	1f

	addi	r4,r4,THREAD	/* want THREAD of last_task_used_spe */

	SAVE_32EVR(0,r10,r4)

	SAVE_32EVRS(0,r10,r4)

   	evxor	evr10, evr10, evr10	/* clear out evr10 */

	evmwumiaa evr10, evr10, evr10	/* evr10 <- ACC = 0 * 0 + ACC */

	li	r5,THREAD_ACC
@@ -873,7 +873,7 @@ load_up_spe: 
	stw	r4,THREAD_USED_SPE(r5)

	evlddx	evr4,r10,r5

	evmra	evr4,evr4

	REST_32EVR(0,r10,r5)

	REST_32EVRS(0,r10,r5)

#ifndef CONFIG_SMP

	subi	r4,r5,THREAD

	stw	r4,last_task_used_spe@l(r3)
@@ -963,7 +963,7 @@ _GLOBAL(giveup_spe) 
	addi	r3,r3,THREAD		/* want THREAD of task */

	lwz	r5,PT_REGS(r3)

	cmpi	0,r5,0

	SAVE_32EVR(0, r4, r3)

	SAVE_32EVRS(0, r4, r3)

   	evxor	evr6, evr6, evr6	/* clear out evr6 */

	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */

	li	r4,THREAD_ACC

include/asm-ppc/ppc_asm.h→include/asm-powerpc/ppc_asm.h

+146 −59
Original line number Diff line number Diff line 
/*

 * include/asm-ppc/ppc_asm.h

 *

 * Definitions used by various bits of low-level assembly code on PowerPC.

 *

 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.

 *

 *  This program is free software; you can redistribute it and/or

 *  modify it under the terms of the GNU General Public License

 *  as published by the Free Software Foundation; either version

 *  2 of the License, or (at your option) any later version.

 */



#include <linux/config.h>

#ifndef _ASM_POWERPC_PPC_ASM_H

#define _ASM_POWERPC_PPC_ASM_H



#ifdef __ASSEMBLY__



/*

 * Macros for storing registers into and loading registers from

 * exception frames.

 */

#ifdef __powerpc64__

#define SAVE_GPR(n, base)	std	n,GPR0+8*(n)(base)

#define REST_GPR(n, base)	ld	n,GPR0+8*(n)(base)

#define SAVE_NVGPRS(base)	SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)

#define REST_NVGPRS(base)	REST_8GPRS(14, base); REST_10GPRS(22, base)

#else

#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)

#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)

#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \

				SAVE_10GPRS(22, base)

#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \

				REST_10GPRS(22, base)

#endif





#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)

#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)

#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)

#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)

#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)

#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)

#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)

#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)

#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)



#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \

				SAVE_10GPRS(22, base)

#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \

				REST_10GPRS(22, base)



#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*(n)(base)

#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)

#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
@@ -47,32 +49,80 @@ 
#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)



#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,b,base

#define SAVE_2VR(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)

#define SAVE_4VR(n,b,base)	SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)

#define SAVE_8VR(n,b,base)	SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)

#define SAVE_16VR(n,b,base)	SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)

#define SAVE_32VR(n,b,base)	SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)

#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)

#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)

#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)

#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)

#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)

#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,b,base

#define REST_2VR(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)

#define REST_4VR(n,b,base)	REST_2VR(n,b,base); REST_2VR(n+2,b,base)

#define REST_8VR(n,b,base)	REST_4VR(n,b,base); REST_4VR(n+4,b,base)

#define REST_16VR(n,b,base)	REST_8VR(n,b,base); REST_8VR(n+8,b,base)

#define REST_32VR(n,b,base)	REST_16VR(n,b,base); REST_16VR(n+16,b,base)

#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)

#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)

#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)

#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)

#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)



#define SAVE_EVR(n,s,base)	evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)

#define SAVE_2EVR(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)

#define SAVE_4EVR(n,s,base)	SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)

#define SAVE_8EVR(n,s,base)	SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)

#define SAVE_16EVR(n,s,base)	SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)

#define SAVE_32EVR(n,s,base)	SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)



#define SAVE_2EVRS(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)

#define SAVE_4EVRS(n,s,base)	SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)

#define SAVE_8EVRS(n,s,base)	SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)

#define SAVE_16EVRS(n,s,base)	SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)

#define SAVE_32EVRS(n,s,base)	SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)

#define REST_EVR(n,s,base)	lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n

#define REST_2EVR(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)

#define REST_4EVR(n,s,base)	REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)

#define REST_8EVR(n,s,base)	REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)

#define REST_16EVR(n,s,base)	REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)

#define REST_32EVR(n,s,base)	REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)

#define REST_2EVRS(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)

#define REST_4EVRS(n,s,base)	REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)

#define REST_8EVRS(n,s,base)	REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)

#define REST_16EVRS(n,s,base)	REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)

#define REST_32EVRS(n,s,base)	REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)



/* Macros to adjust thread priority for Iseries hardware multithreading */

#define HMT_LOW		or 1,1,1

#define HMT_MEDIUM	or 2,2,2

#define HMT_HIGH	or 3,3,3



/* handle instructions that older assemblers may not know */

#define RFCI		.long 0x4c000066	/* rfci instruction */

#define RFDI		.long 0x4c00004e	/* rfdi instruction */

#define RFMCI		.long 0x4c00004c	/* rfmci instruction */



/* 

 * LOADADDR( rn, name )

 *   loads the address of 'name' into 'rn'

 *

 * LOADBASE( rn, name )

 *   loads the address (less the low 16 bits) of 'name' into 'rn'

 *   suitable for base+disp addressing

 */

#ifdef __powerpc64__

#define LOADADDR(rn,name) \

	lis	rn,name##@highest;	\

	ori	rn,rn,name##@higher;	\

	rldicr	rn,rn,32,31;		\

	oris	rn,rn,name##@h;		\

	ori	rn,rn,name##@l



#define LOADBASE(rn,name) \

	lis	rn,name@highest;	\

	ori	rn,rn,name@higher;	\

	rldicr	rn,rn,32,31;		\

	oris	rn,rn,name@ha





#define SET_REG_TO_CONST(reg, value)	         	\

	lis     reg,(((value)>>48)&0xFFFF);             \

	ori     reg,reg,(((value)>>32)&0xFFFF);         \

	rldicr  reg,reg,32,31;                          \

	oris    reg,reg,(((value)>>16)&0xFFFF);         \

	ori     reg,reg,((value)&0xFFFF);



#define SET_REG_TO_LABEL(reg, label)	         	\

	lis     reg,(label)@highest;                    \

	ori     reg,reg,(label)@higher;                 \

	rldicr  reg,reg,32,31;                          \

	oris    reg,reg,(label)@h;                      \

	ori     reg,reg,(label)@l;

#endif



/* various errata or part fixups */

#ifdef CONFIG_PPC601_SYNC_FIX

#define SYNC				\

BEGIN_FTR_SECTION			\
@@ -93,6 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601) 
#define ISYNC_601

#endif





#ifndef CONFIG_SMP

#define TLBSYNC

#else /* CONFIG_SMP */
@@ -104,6 +155,7 @@ BEGIN_FTR_SECTION \ 
END_FTR_SECTION_IFCLR(CPU_FTR_601)

#endif



	

/*

 * This instruction is not implemented on the PPC 603 or 601; however, on

 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
@@ -121,14 +173,44 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
	bdnz	0b

#endif



#ifdef CONFIG_BOOKE



#ifdef CONFIG_IBM405_ERR77

#define PPC405_ERR77(ra,rb)	dcbt	ra, rb;

#define	PPC405_ERR77_SYNC	sync;

#else

#define PPC405_ERR77(ra,rb)

#define PPC405_ERR77_SYNC

#endif





#ifdef CONFIG_IBM440EP_ERR42

#define PPC440EP_ERR42 isync

#else

#define PPC440EP_ERR42

#endif





#if defined(CONFIG_BOOKE)

#define tophys(rd,rs)				\

	addis	rd,rs,0



#define tovirt(rd,rs)				\

	addis	rd,rs,0



#else  /* CONFIG_BOOKE */

#elif defined(CONFIG_PPC64)

/* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,

 * Then we can easily do this with one asm insn. -Peter

 */

#define tophys(rd,rs)                           \

        lis     rd,((KERNELBASE>>48)&0xFFFF);   \

        rldicr  rd,rd,32,31;                    \

        sub     rd,rs,rd



#define tovirt(rd,rs)                           \

        lis     rd,((KERNELBASE>>48)&0xFFFF);   \

        rldicr  rd,rd,32,31;                    \

        add     rd,rs,rd

#else

/*

 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the

 * physical base address of RAM at compile time.
@@ -146,14 +228,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
	.align  1;				\

	.long   0b;				\

	.previous

#endif  /* CONFIG_BOOKE */

#endif



/*

 * On 64-bit cpus, we use the rfid instruction instead of rfi, but

 * we then have to make sure we preserve the top 32 bits except for

 * the 64-bit mode bit, which we clear.

 */

#ifdef CONFIG_PPC64BRIDGE

#if defined(CONFIG_PPC64BRIDGE)

#define	FIX_SRR1(ra, rb)	\

	mr	rb,ra;		\

	mfmsr	ra;		\
@@ -162,6 +244,17 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#define	RFI		.long	0x4c000024	/* rfid instruction */

#define MTMSRD(r)	.long	(0x7c000164 + ((r) << 21))	/* mtmsrd */

#define CLR_TOP32(r)	rlwinm	(r),(r),0,0,31	/* clear top 32 bits */

#elif defined(CONFIG_PPC64)

/* Insert the high 32 bits of the MSR into what will be the new

   MSR (via SRR1 and rfid)  This preserves the MSR.SF and MSR.ISF

   bits. */



#define FIX_SRR1(ra, rb)	\

	mr	rb,ra;		\

	mfmsr	ra;		\

	rldimi	ra,rb,0,32



#define CLR_TOP32(r)	rlwinm	(r),(r),0,0,31	/* clear top 32 bits */



#else

#define FIX_SRR1(ra, rb)
@@ -172,24 +265,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#endif

#define MTMSRD(r)	mtmsr	r

#define CLR_TOP32(r)

#endif /* CONFIG_PPC64BRIDGE */



#define RFCI		.long 0x4c000066	/* rfci instruction */

#define RFDI		.long 0x4c00004e	/* rfdi instruction */

#define RFMCI		.long 0x4c00004c	/* rfmci instruction */



#ifdef CONFIG_IBM405_ERR77

#define PPC405_ERR77(ra,rb)	dcbt	ra, rb;

#define	PPC405_ERR77_SYNC	sync;

#else

#define PPC405_ERR77(ra,rb)

#define PPC405_ERR77_SYNC

#endif



#ifdef CONFIG_IBM440EP_ERR42

#define PPC440EP_ERR42 isync

#else

#define PPC440EP_ERR42

#endif



/* The boring bits... */
@@ -277,6 +352,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#define	fr30	30

#define	fr31	31



/* AltiVec Registers (VPRs) */



#define	vr0	0

#define	vr1	1

#define	vr2	2
@@ -310,6 +387,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#define	vr30	30

#define	vr31	31



/* SPE Registers (EVPRs) */



#define	evr0	0

#define	evr1	1

#define	evr2	2
@@ -348,3 +427,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#define N_RSYM	64

#define N_SLINE	68

#define N_SO	100



#define ASM_CONST(x) x

#else

  #define __ASM_CONST(x) x##UL

  #define ASM_CONST(x) __ASM_CONST(x)

#endif /*  __ASSEMBLY__ */



#endif /* _ASM_POWERPC_PPC_ASM_H */

include/asm-ppc64/cputable.h

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
#define __ASM_PPC_CPUTABLE_H



#include <linux/config.h>

#include <asm/page.h> /* for ASM_CONST */

#include <asm/ppc_asm.h> /* for ASM_CONST */



/* Exposed to userland CPU features - Must match ppc32 definitions */

#define PPC_FEATURE_32			0x80000000

include/asm-ppc64/mmu.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#define _PPC64_MMU_H_



#include <linux/config.h>

#include <asm/ppc_asm.h> /* for ASM_CONST */

#include <asm/page.h>



/*