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Commit 5f1f3d50 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
Browse files

arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range 



The ranges DT entry needed by the PCIe controller is defined at the
SoC .dtsi level. However, some boards have a NOR flash, and to support
it, they need to override the SoC-level ranges property to add an
additional range. Since PCIe and NOR support came separately, some
boards were not properly changed to include the PCIe range in their
ranges property at the .dts level.

This commit fixes those platforms.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 4089fe95

arch/arm/boot/dts/armada-xp-gp.dts

+3 −2
Original line number Diff line number Diff line
@@ -39,8 +39,9 @@ 
	};



	soc {

		ranges = <0          0 0xd0000000 0x100000

			  0xf0000000 0 0xf0000000 0x1000000>;

		ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */

			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */

			  0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;



		internal-regs {

			serial@12000 {

arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts

+3 −2
Original line number Diff line number Diff line
@@ -27,8 +27,9 @@ 
	};



	soc {

		ranges = <0          0 0xd0000000 0x100000

			  0xf0000000 0 0xf0000000 0x8000000>;

		ranges = <0          0 0xd0000000 0x100000	/* Internal registers 1MiB */

			  0xe0000000 0 0xe0000000 0x8100000     /* PCIe */

			  0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;



		internal-regs {

			serial@12000 {