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Commit 5eb26c60 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Maxime Coquelin
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ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 



Use a generic name for this kind of PLL

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
parent 0a8c739c

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+2 −2
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@ Required properties: 
	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_1",	"st,clkgen-plls-c32"

	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"

	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"



	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"

	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"

arch/arm/boot/dts/stih407-clock.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ 


			clk_s_c0_pll0: clk-s-c0-pll0 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;
@@ -143,7 +143,7 @@ 


			clk_s_c0_pll1: clk-s-c0-pll1 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;

arch/arm/boot/dts/stih410-clock.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ 


			clk_s_c0_pll0: clk-s-c0-pll0 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@ 


			clk_s_c0_pll1: clk-s-c0-pll1 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;

arch/arm/boot/dts/stih418-clock.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ 


			clk_s_c0_pll0: clk-s-c0-pll0 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@ 


			clk_s_c0_pll1: clk-s-c0-pll1 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;