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Commit 5db94019 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make IS_GEN macros only take dev_priv 



Saves 1416 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476352990-2504-1-git-send-email-tvrtko.ursulin@linux.intel.com
parent 55b8f2a7

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -4558,7 +4558,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 
	else if (IS_VALLEYVIEW(dev_priv))

	else if (IS_VALLEYVIEW(dev_priv))

		num_levels = 1;

		num_levels = 1;

	else

	else

		num_levels = ilk_wm_max_level(dev) + 1;

		num_levels = ilk_wm_max_level(dev_priv) + 1;





	drm_modeset_lock_all(dev);

	drm_modeset_lock_all(dev);
@@ -4674,7 +4674,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 
	else if (IS_VALLEYVIEW(dev_priv))

	else if (IS_VALLEYVIEW(dev_priv))

		num_levels = 1;

		num_levels = 1;

	else

	else

		num_levels = ilk_wm_max_level(dev) + 1;

		num_levels = ilk_wm_max_level(dev_priv) + 1;





	if (len >= sizeof(tmp))

	if (len >= sizeof(tmp))

		return -EINVAL;

		return -EINVAL;

drivers/gpu/drm/i915/i915_drv.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev) 
			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_IBX;

				dev_priv->pch_type = PCH_IBX;

				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

				WARN_ON(!IS_GEN5(dev));

				WARN_ON(!IS_GEN5(dev_priv));

			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {

			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_CPT;

				dev_priv->pch_type = PCH_CPT;

				DRM_DEBUG_KMS("Found CougarPoint PCH\n");

				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
@@ -860,7 +860,7 @@ static int i915_mmio_setup(struct drm_device *dev) 
	int mmio_bar;

	int mmio_bar;

	int mmio_size;

	int mmio_size;





	mmio_bar = IS_GEN2(dev) ? 1 : 0;

	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;

	/*

	/*

	 * Before gen4, the registers and the GTT are behind different BARs.

	 * Before gen4, the registers and the GTT are behind different BARs.

	 * However, from gen4 onwards, the registers and the GTT are shared

	 * However, from gen4 onwards, the registers and the GTT are shared
@@ -1013,7 +1013,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 
	pci_set_master(pdev);

	pci_set_master(pdev);





	/* overlay on gen2 is broken and can't address above 1G */

	/* overlay on gen2 is broken and can't address above 1G */

	if (IS_GEN2(dev)) {

	if (IS_GEN2(dev_priv)) {

		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));

		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));

		if (ret) {

		if (ret) {

			DRM_ERROR("failed to set DMA mask\n");

			DRM_ERROR("failed to set DMA mask\n");

drivers/gpu/drm/i915/i915_drv.h

+8 −8
Original line number Original line Diff line number Diff line
@@ -2738,14 +2738,14 @@ struct drm_i915_cmd_table { 
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular

 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular

 * chips, etc.).

 * chips, etc.).

 */

 */

#define IS_GEN2(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(1)))

#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))

#define IS_GEN3(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(2)))

#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))

#define IS_GEN4(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(3)))

#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))

#define IS_GEN5(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(4)))

#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))

#define IS_GEN6(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(5)))

#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))

#define IS_GEN7(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(6)))

#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))

#define IS_GEN8(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(7)))

#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))

#define IS_GEN9(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(8)))

#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))





#define ENGINE_MASK(id)	BIT(id)

#define ENGINE_MASK(id)	BIT(id)

#define RENDER_RING	ENGINE_MASK(RCS)

#define RENDER_RING	ENGINE_MASK(RCS)

drivers/gpu/drm/i915/i915_gem.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -4375,15 +4375,15 @@ void i915_gem_init_swizzling(struct drm_device *dev) 
	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |

				 DISP_TILE_SURFACE_SWIZZLING);

				 DISP_TILE_SURFACE_SWIZZLING);





	if (IS_GEN5(dev))

	if (IS_GEN5(dev_priv))

		return;

		return;





	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);

	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);

	if (IS_GEN6(dev))

	if (IS_GEN6(dev_priv))

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));

	else if (IS_GEN7(dev))

	else if (IS_GEN7(dev_priv))

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));

	else if (IS_GEN8(dev))

	else if (IS_GEN8(dev_priv))

		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));

		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));

	else

	else

		BUG();

		BUG();

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 
				   struct drm_i915_gem_relocation_entry *reloc,

				   struct drm_i915_gem_relocation_entry *reloc,

				   struct reloc_cache *cache)

				   struct reloc_cache *cache)

{

{

	struct drm_device *dev = obj->base.dev;

	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);

	struct drm_gem_object *target_obj;

	struct drm_gem_object *target_obj;

	struct drm_i915_gem_object *target_i915_obj;

	struct drm_i915_gem_object *target_i915_obj;

	struct i915_vma *target_vma;

	struct i915_vma *target_vma;
@@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 
	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and

	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and

	 * pipe_control writes because the gpu doesn't properly redirect them

	 * pipe_control writes because the gpu doesn't properly redirect them

	 * through the ppgtt for non_secure batchbuffers. */

	 * through the ppgtt for non_secure batchbuffers. */

	if (unlikely(IS_GEN6(dev) &&

	if (unlikely(IS_GEN6(dev_priv) &&

	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {

	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {

		ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,

		ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,

				    PIN_GLOBAL);

				    PIN_GLOBAL);