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Commit 5d9657d8 authored by Claudiu Manoil's avatar Claudiu Manoil Committed by David S. Miller
Browse files

gianfar: Remove redundant programming of [rt]xic registers 



For Multi Q Multi Group (MQ_MG_MODE) mode, the Rx/Tx colescing registers [rt]xic
are aliased with the [rt]xic0 registers (coalescing setting regs for Q0). This
avoids programming twice in a row the coalescing registers for the Rx/Tx hw Q0.

Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6be5ed3f

drivers/net/ethernet/freescale/gianfar.c

+12 −12
Original line number Diff line number Diff line
@@ -1821,20 +1821,9 @@ void gfar_configure_coalescing(struct gfar_private *priv, 
{

	struct gfar __iomem *regs = priv->gfargrp[0].regs;

	u32 __iomem *baddr;

	int i = 0;



	/* Backward compatible case ---- even if we enable

	 * multiple queues, there's only single reg to program

	 */

	gfar_write(&regs->txic, 0);

	if (likely(priv->tx_queue[0]->txcoalescing))

		gfar_write(&regs->txic, priv->tx_queue[0]->txic);



	gfar_write(&regs->rxic, 0);

	if (unlikely(priv->rx_queue[0]->rxcoalescing))

		gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);



	if (priv->mode == MQ_MG_MODE) {

		int i = 0;

		baddr = &regs->txic0;

		for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {

			gfar_write(baddr + i, 0);
@@ -1848,6 +1837,17 @@ void gfar_configure_coalescing(struct gfar_private *priv, 
			if (likely(priv->rx_queue[i]->rxcoalescing))

				gfar_write(baddr + i, priv->rx_queue[i]->rxic);

		}

	} else {

		/* Backward compatible case ---- even if we enable

		 * multiple queues, there's only single reg to program

		 */

		gfar_write(&regs->txic, 0);

		if (likely(priv->tx_queue[0]->txcoalescing))

			gfar_write(&regs->txic, priv->tx_queue[0]->txic);



		gfar_write(&regs->rxic, 0);

		if (unlikely(priv->rx_queue[0]->rxcoalescing))

			gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);

	}

}