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Commit 5c6366e1 authored by Murthy, Raghuveer's avatar Murthy, Raghuveer Committed by Tomi Valkeinen
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OMAP: DSS2: Adding dss_features for independent core clk divider 



In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.

In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.

The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 85604b0a

drivers/video/omap2/dss/dss_features.c

+2 −1
Original line number Diff line number Diff line
@@ -234,7 +234,8 @@ static struct omap_dss_features omap4_dss_features = { 


	.has_feature	=

		FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |

		FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1,

		FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |

		FEAT_CORE_CLK_DIV,



	.num_mgrs = 3,

	.num_ovls = 3,

drivers/video/omap2/dss/dss_features.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ enum dss_feat_id { 
	FEAT_LINEBUFFERSPLIT	= 1 << 8,

	FEAT_ROWREPEATENABLE	= 1 << 9,

	FEAT_RESIZECONF		= 1 << 10,

	/* Independent core clk divider */

	FEAT_CORE_CLK_DIV	= 1 << 11,

};



/* DSS register field id */