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Commit 5c1c63f6 authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
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clk: rockchip: add 533.25MHz to rk3399 clock rates table 



We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1001354c

drivers/clk/rockchip/clk-rk3399.c

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 
	RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),

	RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),

	RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),

	RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),

	RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),

	RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),

	RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),