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Commit 5b9adbd3 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Some additional patches for radeon for 3.16 now that -fixes has been merged.

- Gart fix for all asics r6xx+
- Add some VM tuning parameters
- misc fixes

* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
  drm/radeon/dpm: powertune updates for SI
  Revert "drm/radeon: use variable UVD clocks"
  drm/radeon: add query for number of active CUs
  drm/radeon: add debugfs file to trigger GPU reset
  drm/radeon: make vm_block_size a module parameter
  drm/radeon: make VM size a module parameter (v2)
  drm/radeon: rename alt_domain to allowed_domains
  drm/radeon: use the SDMA on for buffer moves on CIK again
  drm/radeon: remove range check from *_gart_set_page
  drm/radeon: stop poisoning the GART TLB
  drm/radeon: hdmi deep color modes must obey clock limit of sink.
  drm/edid: Store all supported hdmi deep color modes in drm_display_info
  drm/radeon: add missing vce init case for hawaii
  drm/radeon: use lower_32_bits where appropriate
parents f95aeb17 685d54b3

drivers/gpu/drm/drm_edid.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -3471,18 +3471,21 @@ static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 




			if (hdmi[6] & DRM_EDID_HDMI_DC_30) {

			if (hdmi[6] & DRM_EDID_HDMI_DC_30) {

				dc_bpc = 10;

				dc_bpc = 10;

				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;

				DRM_DEBUG("%s: HDMI sink does deep color 30.\n",

				DRM_DEBUG("%s: HDMI sink does deep color 30.\n",

						  connector->name);

						  connector->name);

			}

			}





			if (hdmi[6] & DRM_EDID_HDMI_DC_36) {

			if (hdmi[6] & DRM_EDID_HDMI_DC_36) {

				dc_bpc = 12;

				dc_bpc = 12;

				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;

				DRM_DEBUG("%s: HDMI sink does deep color 36.\n",

				DRM_DEBUG("%s: HDMI sink does deep color 36.\n",

						  connector->name);

						  connector->name);

			}

			}





			if (hdmi[6] & DRM_EDID_HDMI_DC_48) {

			if (hdmi[6] & DRM_EDID_HDMI_DC_48) {

				dc_bpc = 16;

				dc_bpc = 16;

				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;

				DRM_DEBUG("%s: HDMI sink does deep color 48.\n",

				DRM_DEBUG("%s: HDMI sink does deep color 48.\n",

						  connector->name);

						  connector->name);

			}

			}

drivers/gpu/drm/radeon/atombios_crtc.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -962,6 +962,9 @@ static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_ 
		struct radeon_connector_atom_dig *dig_connector =

		struct radeon_connector_atom_dig *dig_connector =

			radeon_connector->con_priv;

			radeon_connector->con_priv;

		int dp_clock;

		int dp_clock;



		/* Assign mode clock for hdmi deep color max clock limit check */

		radeon_connector->pixelclock_for_modeset = mode->clock;

		radeon_crtc->bpc = radeon_get_monitor_bpc(connector);

		radeon_crtc->bpc = radeon_get_monitor_bpc(connector);





		switch (encoder_mode) {

		switch (encoder_mode) {

drivers/gpu/drm/radeon/cik.c

+14 −4
Original line number Original line Diff line number Diff line
@@ -80,6 +80,7 @@ extern int sumo_rlc_init(struct radeon_device *rdev); 
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);

extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);

extern void si_rlc_reset(struct radeon_device *rdev);

extern void si_rlc_reset(struct radeon_device *rdev);

extern void si_init_uvd_internal_cg(struct radeon_device *rdev);

extern void si_init_uvd_internal_cg(struct radeon_device *rdev);

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

extern int cik_sdma_resume(struct radeon_device *rdev);

extern int cik_sdma_resume(struct radeon_device *rdev);

extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);

extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);

extern void cik_sdma_fini(struct radeon_device *rdev);

extern void cik_sdma_fini(struct radeon_device *rdev);
@@ -3257,7 +3258,7 @@ static void cik_gpu_init(struct radeon_device *rdev) 
	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 hdp_host_path_cntl;

	u32 hdp_host_path_cntl;

	u32 tmp;

	u32 tmp;

	int i, j;

	int i, j, k;





	switch (rdev->family) {

	switch (rdev->family) {

	case CHIP_BONAIRE:

	case CHIP_BONAIRE:
@@ -3446,6 +3447,15 @@ static void cik_gpu_init(struct radeon_device *rdev) 
		     rdev->config.cik.max_sh_per_se,

		     rdev->config.cik.max_sh_per_se,

		     rdev->config.cik.max_backends_per_se);

		     rdev->config.cik.max_backends_per_se);





	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

			for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {

				rdev->config.cik.active_cus +=

					hweight32(cik_get_cu_active_bitmap(rdev, i, j));

			}

		}

	}



	/* set HW defaults for 3D engine */

	/* set HW defaults for 3D engine */

	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));

	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
@@ -3698,7 +3708,7 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, 
	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;

	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;





	radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

	radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

	radeon_ring_write(ring, addr & 0xffffffff);

	radeon_ring_write(ring, lower_32_bits(addr));

	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);

	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);





	return true;

	return true;
@@ -3818,7 +3828,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 
			radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

			radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

			radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));

			radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));

			radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

			radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

			radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);

			radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

			radeon_ring_write(ring, next_rptr);

			radeon_ring_write(ring, next_rptr);

		}

		}
@@ -5446,7 +5456,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	       (u32)(rdev->dummy_page.addr >> 12));

	       (u32)(rdev->dummy_page.addr >> 12));

	WREG32(VM_CONTEXT1_CNTL2, 4);

	WREG32(VM_CONTEXT1_CNTL2, 4);

	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

				PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |

				PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |

				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

drivers/gpu/drm/radeon/cik_sdma.c

+13 −13
Original line number Original line Diff line number Diff line
@@ -141,7 +141,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 
		next_rptr += 4;

		next_rptr += 4;

		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);

		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

		radeon_ring_write(ring, 1); /* number of DWs to follow */

		radeon_ring_write(ring, 1); /* number of DWs to follow */

		radeon_ring_write(ring, next_rptr);

		radeon_ring_write(ring, next_rptr);

	}

	}
@@ -151,7 +151,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 
		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));

	radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */

	radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */

	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);

	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));

	radeon_ring_write(ring, ib->length_dw);

	radeon_ring_write(ring, ib->length_dw);





}

}
@@ -203,8 +203,8 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 




	/* write the fence */

	/* write the fence */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));

	radeon_ring_write(ring, addr & 0xffffffff);

	radeon_ring_write(ring, lower_32_bits(addr));

	radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	radeon_ring_write(ring, upper_32_bits(addr));

	radeon_ring_write(ring, fence->seq);

	radeon_ring_write(ring, fence->seq);

	/* generate an interrupt */

	/* generate an interrupt */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
@@ -233,7 +233,7 @@ bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 




	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));

	radeon_ring_write(ring, addr & 0xfffffff8);

	radeon_ring_write(ring, addr & 0xfffffff8);

	radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	radeon_ring_write(ring, upper_32_bits(addr));





	return true;

	return true;

}

}
@@ -551,10 +551,10 @@ int cik_copy_dma(struct radeon_device *rdev, 
		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));

		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));

		radeon_ring_write(ring, cur_size_in_bytes);

		radeon_ring_write(ring, cur_size_in_bytes);

		radeon_ring_write(ring, 0); /* src/dst endian swap */

		radeon_ring_write(ring, 0); /* src/dst endian swap */

		radeon_ring_write(ring, src_offset & 0xffffffff);

		radeon_ring_write(ring, lower_32_bits(src_offset));

		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);

		radeon_ring_write(ring, upper_32_bits(src_offset));

		radeon_ring_write(ring, dst_offset & 0xffffffff);

		radeon_ring_write(ring, lower_32_bits(dst_offset));

		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);

		radeon_ring_write(ring, upper_32_bits(dst_offset));

		src_offset += cur_size_in_bytes;

		src_offset += cur_size_in_bytes;

		dst_offset += cur_size_in_bytes;

		dst_offset += cur_size_in_bytes;

	}

	}
@@ -605,7 +605,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev, 
	}

	}

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

	radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);

	radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);

	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);

	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));

	radeon_ring_write(ring, 1); /* number of DWs to follow */

	radeon_ring_write(ring, 1); /* number of DWs to follow */

	radeon_ring_write(ring, 0xDEADBEEF);

	radeon_ring_write(ring, 0xDEADBEEF);

	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring);
@@ -660,7 +660,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 




	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);

	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);

	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;

	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;

	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;

	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);

	ib.ptr[3] = 1;

	ib.ptr[3] = 1;

	ib.ptr[4] = 0xDEADBEEF;

	ib.ptr[4] = 0xDEADBEEF;

	ib.length_dw = 5;

	ib.length_dw = 5;
@@ -752,9 +752,9 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
			ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);

			ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);

			ib->ptr[ib->length_dw++] = bytes;

			ib->ptr[ib->length_dw++] = bytes;

			ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */

			ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */

			ib->ptr[ib->length_dw++] = src & 0xffffffff;

			ib->ptr[ib->length_dw++] = lower_32_bits(src);

			ib->ptr[ib->length_dw++] = upper_32_bits(src);

			ib->ptr[ib->length_dw++] = upper_32_bits(src);

			ib->ptr[ib->length_dw++] = pe & 0xffffffff;

			ib->ptr[ib->length_dw++] = lower_32_bits(pe);

			ib->ptr[ib->length_dw++] = upper_32_bits(pe);

			ib->ptr[ib->length_dw++] = upper_32_bits(pe);





			pe += bytes;

			pe += bytes;

drivers/gpu/drm/radeon/evergreen.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -3337,6 +3337,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
			disabled_rb_mask &= ~(1 << i);

			disabled_rb_mask &= ~(1 << i);

	}

	}





	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {

		u32 simd_disable_bitmap;



		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

		simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;

		tmp <<= 16;

		tmp |= simd_disable_bitmap;

	}

	rdev->config.evergreen.active_simds = hweight32(~tmp);



	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);