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Commit 5b544337 authored Jul 06, 2018 by Chris Wilson

drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL

Replace the magic bit with the proper symbolic name for instructing
MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT
address (still virtual!) on gen4+.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706142323.25699-1-chris@chris-wilson.co.uk

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

parent 207b7000

drivers/gpu/drm/i915/selftests/huge_pages.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
		*cmd++ = val;
		} else if (gen >= 4) {
		*cmd++ = MI_STORE_DWORD_IMM_GEN4 \|
		(gen < 6 ? 1 << 22 : 0);
		(gen < 6 ? MI_USE_GGTT : 0);
		*cmd++ = 0;
		*cmd++ = offset;
		*cmd++ = val;
		} else {
		*cmd++ = MI_STORE_DWORD_IMM \| 1 << 22;
		*cmd++ = MI_STORE_DWORD_IMM \| MI_MEM_VIRTUAL;
		*cmd++ = offset;
		*cmd++ = val;
		}

drivers/gpu/drm/i915/selftests/i915_gem_coherency.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
		*cs++ = v;
		} else if (INTEL_GEN(i915) >= 4) {
		*cs++ = MI_STORE_DWORD_IMM_GEN4 \| 1 << 22;
		*cs++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;
		*cs++ = 0;
		*cs++ = i915_ggtt_offset(vma) + offset;
		*cs++ = v;
		} else {
		*cs++ = MI_STORE_DWORD_IMM \| 1 << 22;
		*cs++ = MI_STORE_DWORD_IMM \| MI_MEM_VIRTUAL;
		*cs++ = i915_ggtt_offset(vma) + offset;
		*cs++ = v;
		*cs++ = MI_NOOP;

drivers/gpu/drm/i915/selftests/i915_gem_context.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
		*cmd++ = value;
		} else if (gen >= 4) {
		*cmd++ = MI_STORE_DWORD_IMM_GEN4 \|
		(gen < 6 ? 1 << 22 : 0);
		(gen < 6 ? MI_USE_GGTT : 0);
		*cmd++ = 0;
		*cmd++ = offset;
		*cmd++ = value;
		} else {
		*cmd++ = MI_STORE_DWORD_IMM \| 1 << 22;
		*cmd++ = MI_STORE_DWORD_IMM \| MI_MEM_VIRTUAL;
		*cmd++ = offset;
		*cmd++ = value;
		}

drivers/gpu/drm/i915/selftests/intel_hangcheck.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h,
		*batch++ = MI_BATCH_BUFFER_START \| 1 << 8;
		*batch++ = lower_32_bits(vma->node.start);
		} else if (INTEL_GEN(i915) >= 4) {
		*batch++ = MI_STORE_DWORD_IMM_GEN4 \| 1 << 22;
		*batch++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;
		*batch++ = 0;
		*batch++ = lower_32_bits(hws_address(hws, rq));
		*batch++ = rq->fence.seqno;