Commit 5b33139b authored Apr 23, 2018 by Martin Blumenstingl Committed by Jerome Brunet Apr 25, 2018

clk: meson: meson8b: fix meson8b_cpu_clk parent clock name



meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel

The name of the "xtal" clock parent is specified correctly. However,
there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
(which matches the name from the datasheet). However, the mux parent
definition uses the name "cpu_out_sel" which does not match any existing
clock.

Fixes: 251b6fd3 ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

parent b251e4c8

drivers/clk/meson/meson8b.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = {
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = (const char *[]){ "xtal", "cpu_out_sel" },
		.parent_names = (const char *[]){ "xtal",
		"cpu_scale_out_sel" },
		.num_parents = 2,
		.flags = (CLK_SET_RATE_PARENT \|
		CLK_SET_RATE_NO_REPARENT),