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Commit 597667d8 authored by Gregory CLEMENT's avatar Gregory CLEMENT
Browse files

ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes 



This extra clock is needed to access the registers of the UARTs used on
CP110 component of the Armada 7K/8K SoCs.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent 41d63e45

arch/arm64/boot/dts/marvell/armada-cp110.dtsi

+12 −4
Original line number Diff line number Diff line
@@ -303,7 +303,9 @@ 
			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			clock-names = "baudclk", "apb_pclk";

			clocks = <&CP110_LABEL(clk) 1 21>,

				 <&CP110_LABEL(clk) 1 17>;

			status = "disabled";

		};
@@ -313,7 +315,9 @@ 
			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			clock-names = "baudclk", "apb_pclk";

			clocks = <&CP110_LABEL(clk) 1 21>,

				 <&CP110_LABEL(clk) 1 17>;

			status = "disabled";

		};
@@ -323,7 +327,9 @@ 
			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			clock-names = "baudclk", "apb_pclk";

			clocks = <&CP110_LABEL(clk) 1 21>,

				 <&CP110_LABEL(clk) 1 17>;

			status = "disabled";

		};
@@ -333,7 +339,9 @@ 
			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			clock-names = "baudclk", "apb_pclk";

			clocks = <&CP110_LABEL(clk) 1 21>,

				 <&CP110_LABEL(clk) 1 17>;

			status = "disabled";

		};