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Commit 5846581e authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
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locking/memory-barriers.txt: Fix broken DMA vs. MMIO ordering example 



The section of memory-barriers.txt that describes the dma_Xmb() barriers
has an incorrect example claiming that a wmb() is required after writing
to coherent memory in order for those writes to be visible to a device
before a subsequent MMIO access using writel() can reach the device.

In fact, this ordering guarantee is provided (at significant cost on some
architectures such as arm and power) by writel, so the wmb() is not
necessary. writel_relaxed exists for cases where this ordering is not
required.

Fix the example and update the text to make this clearer.

Reported-by: default avatarSinan Kaya <okaya@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: akiyks@gmail.com
Cc: boqun.feng@gmail.com
Cc: dhowells@redhat.com
Cc: j.alglave@ucl.ac.uk
Cc: linux-arch@vger.kernel.org
Cc: luc.maranget@inria.fr
Cc: npiggin@gmail.com
Cc: parri.andrea@gmail.com
Cc: stern@rowland.harvard.edu
Link: http://lkml.kernel.org/r/1526338533-6044-1-git-send-email-paulmck@linux.vnet.ibm.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 371b3269

Documentation/memory-barriers.txt

+9 −8
Original line number Diff line number Diff line
@@ -1920,9 +1920,6 @@ There are some more advanced barrier functions: 
		/* assign ownership */

		desc->status = DEVICE_OWN;



		/* force memory to sync before notifying device via MMIO */

		wmb();



		/* notify device of new descriptors */

		writel(DESC_NOTIFY, doorbell);

	}
@@ -1930,11 +1927,15 @@ There are some more advanced barrier functions: 
     The dma_rmb() allows us guarantee the device has released ownership

     before we read the data from the descriptor, and the dma_wmb() allows

     us to guarantee the data is written to the descriptor before the device

     can see it now has ownership.  The wmb() is needed to guarantee that the

     cache coherent memory writes have completed before attempting a write to

     the cache incoherent MMIO region.



     See Documentation/DMA-API.txt for more information on consistent memory.

     can see it now has ownership.  Note that, when using writel(), a prior

     wmb() is not needed to guarantee that the cache coherent memory writes

     have completed before writing to the MMIO region.  The cheaper

     writel_relaxed() does not provide this guarantee and must not be used

     here.



     See the subsection "Kernel I/O barrier effects" for more information on

     relaxed I/O accessors and the Documentation/DMA-API.txt file for more

     information on consistent memory.





MMIO WRITE BARRIER