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Commit 57ef5798 authored by Neil Armstrong's avatar Neil Armstrong Committed by Kevin Hilman
Browse files

ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL



The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs.

The node is simply added in the meson-gxbb.dtsi file.

For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this
patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
dtsi files.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[khilman: s/MALI/Mali in changelog]
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent ca02e3f9
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+37 −0
Original line number Diff line number Diff line
@@ -443,6 +443,43 @@
	};
};

&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
				       <666666666>,
				       <0>; /* Do Nothing */
	};
};

&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};
+43 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2017 BayLibre SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
				       <666666666>,
				       <0>; /* Do Nothing */
	};
};
+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@
 */

#include "meson-gxl.dtsi"
#include "meson-gxl-mali.dtsi"

/ {
	compatible = "amlogic,s905d", "amlogic,meson-gxl";
+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@
 */

#include "meson-gxl.dtsi"
#include "meson-gxl-mali.dtsi"

/ {
	compatible = "amlogic,s905x", "amlogic,meson-gxl";