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Commit 57e363b8 authored by Brian Norris's avatar Brian Norris
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Merge tag 'nand/for-4.12' of github.com:linux-nand/linux into MTD

From Boris:
"""
This pull request contains:

 - some minor fixes/improvements on existing drivers (fsmc, gpio, ifc,
   davinci, brcmnand, omap)
 - a huge cleanup/rework of the denali driver accompanied with core
   fixes/improvements to simplify the driver code
 - a complete rewrite of the atmel driver to support new DT bindings
   make future evolution easier
 - the addition of per-vendor detection/initialization steps to avoid
   extending the nand_ids table with more extended-id entries
"""
parents da4b1caa 9d2ee0a6
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+106 −1
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Atmel NAND flash
Atmel NAND flash controller bindings

The NAND flash controller node should be defined under the EBI bus (see
Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
One or several NAND devices can be defined under this NAND controller.
The NAND controller might be connected to an ECC engine.

* NAND controller bindings:

Required properties:
- compatible: should be one of the following
	"atmel,at91rm9200-nand-controller"
	"atmel,at91sam9260-nand-controller"
	"atmel,at91sam9261-nand-controller"
	"atmel,at91sam9g45-nand-controller"
	"atmel,sama5d3-nand-controller"
- ranges: empty ranges property to forward EBI ranges definitions.
- #address-cells: should be set to 2.
- #size-cells: should be set to 1.
- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
		controllers.
- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
		  controllers.

Optional properties:
- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
	      a PMECC engine.

* NAND device/chip bindings:

Required properties:
- reg: describes the CS lines assigned to the NAND device. If the NAND device
       exposes multiple CS lines (multi-dies chips), your reg property will
       contain X tuples of 3 entries.
       1st entry: the CS line this NAND chip is connected to
       2nd entry: the base offset of the memory region assigned to this
		  device (always 0)
       3rd entry: the memory region size (always 0x800000)

Optional properties:
- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
- cs-gpios: the GPIO(s) used to control the CS line.
- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
	    on sama5 SoCs.

All generic properties described in
Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
device node, and NAND partitions should be defined under the NAND node as
described in Documentation/devicetree/bindings/mtd/partition.txt.

* ECC engine (PMECC) bindings:

Required properties:
- compatible: should be one of the following
	"atmel,at91sam9g45-pmecc"
	"atmel,sama5d4-pmecc"
	"atmel,sama5d2-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
       block, and the second one to the PMECC_ERRLOC block.

Example:

	pmecc: ecc-engine@ffffc070 {
		compatible = "atmel,at91sam9g45-pmecc";
                reg = <0xffffc070 0x490>,
                      <0xffffc500 0x100>;
	};

	ebi: ebi@10000000 {
		compatible = "atmel,sama5d3-ebi";
		#address-cells = <2>;
		#size-cells = <1>;
		atmel,smc = <&hsmc>;
		reg = <0x10000000 0x10000000
		       0x40000000 0x30000000>;
		ranges = <0x0 0x0 0x10000000 0x10000000
			  0x1 0x0 0x40000000 0x10000000
			  0x2 0x0 0x50000000 0x10000000
			  0x3 0x0 0x60000000 0x10000000>;
		clocks = <&mck>;

                nand_controller: nand-controller {
			compatible = "atmel,sama5d3-nand-controller";
			atmel,nfc-sram = <&nfc_sram>;
			atmel,nfc-io = <&nfc_io>;
			ecc-engine = <&pmecc>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges;

			nand@3 {
				reg = <0x3 0x0 0x800000>;
				atmel,rb = <0>;

				/*
				 * Put generic NAND/MTD properties and
				 * subnodes here.
				 */
			};
		};
	};

-----------------------------------------------------------------------

Deprecated bindings (should not be used in new device trees):

Required properties:
- compatible: The possible values are:
+3 −4
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* Denali NAND controller

Required properties:
  - compatible : should be "denali,denali-nand-dt"
  - compatible : should be one of the following:
      "altr,socfpga-denali-nand"            - for Altera SOCFPGA
  - reg : should contain registers location and length for data and reg.
  - reg-names: Should contain the reg names "nand_data" and "denali_reg"
  - interrupts : The interrupt number.
  - dm-mask : DMA bit mask

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
@@ -15,9 +15,8 @@ Examples:
nand: nand@ff900000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "denali,denali-nand-dt";
	compatible = "altr,socfpga-denali-nand";
	reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
	reg-names = "nand_data", "denali_reg";
	interrupts = <0 144 4>;
	dma-mask = <0xffffffff>;
};
+1 −1
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@@ -2244,7 +2244,7 @@ M: Wenyou Yang <wenyou.yang@atmel.com>
M:	Josh Wu <rainyfeeling@outlook.com>
L:	linux-mtd@lists.infradead.org
S:	Supported
F:	drivers/mtd/nand/atmel_nand*
F:	drivers/mtd/nand/atmel/*

ATMEL SDMMC DRIVER
M:	Ludovic Desroches <ludovic.desroches@microchip.com>
+0 −1
Original line number Diff line number Diff line
@@ -136,7 +136,6 @@ config ETRAX_NANDFLASH
	bool "NAND flash support"
	depends on ETRAX_ARCH_V32
	select MTD_NAND
	select MTD_NAND_IDS
	help
	  This option enables MTD mapping of NAND flash devices.  Needed to use
	  NAND flash memories.  If unsure, say Y.
+1 −1
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@@ -115,7 +115,7 @@ config FSL_CORENET_CF

config FSL_IFC
	bool
	depends on FSL_SOC || ARCH_LAYERSCAPE
	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A

config JZ4780_NEMC
	bool "Ingenic JZ4780 SoC NEMC driver"
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