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Commit 57c78e35 authored by Yong Shen's avatar Yong Shen Committed by Liam Girdwood
Browse files

Change the register name definitions for mc13783 



To make mc13783 and mc13892 share code, the register names should be
changed to fit the new macro definitions in the comming patch.

Signed-off-by: default avatarYong Shen <yong.shen@linaro.org>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Acked-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarLiam Girdwood <lrg@slimlogic.co.uk>
parent a1e516e3

arch/arm/mach-imx/mach-pcm038.c

+2 −2
Original line number Diff line number Diff line
@@ -254,10 +254,10 @@ static struct regulator_init_data cam_data = { 


static struct mc13783_regulator_init_data pcm038_regulators[] = {

	{

		.id = MC13783_REGU_VCAM,

		.id = MC13783_REG_VCAM,

		.init_data = &cam_data,

	}, {

		.id = MC13783_REGU_VMMC1,

		.id = MC13783_REG_VMMC1,

		.init_data = &sdhc1_data,

	},

};

arch/arm/mach-mx3/mach-mx31_3ds.c

+2 −2
Original line number Diff line number Diff line
@@ -140,10 +140,10 @@ static struct regulator_init_data gpo_init = { 


static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {

	{

		.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */

		.id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */

		.init_data = &pwgtx_init,

	}, {

		.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */

		.id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */

		.init_data = &pwgtx_init,

	}, {

arch/arm/mach-mx3/mach-mx31moboard.c

+2 −2
Original line number Diff line number Diff line
@@ -216,11 +216,11 @@ static struct regulator_init_data cam_vreg_data = { 


static struct mc13783_regulator_init_data moboard_regulators[] = {

	{

		.id = MC13783_REGU_VMMC1,

		.id = MC13783_REG_VMMC1,

		.init_data = &sdhc_vreg_data,

	},

	{

		.id = MC13783_REGU_VCAM,

		.id = MC13783_REG_VCAM,

		.init_data = &cam_vreg_data,

	},

};

drivers/regulator/mc13783-regulator.c

+15 −15
Original line number Diff line number Diff line
@@ -228,15 +228,15 @@ static struct regulator_ops mc13783_gpo_regulator_ops; 
	}



#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages)		\

	MC13783_DEFINE(SW, _name, _reg, _vsel_reg, _voltages)

	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)

#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages)		\

	MC13783_DEFINE(REGU, _name, _reg, _vsel_reg, _voltages)

	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)



static struct mc13783_regulator mc13783_regulators[] = {

	MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),



	MC13783_FIXED_DEFINE(REGU, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),

	MC13783_FIXED_DEFINE(REGU, VIOHI, REGULATORMODE0, mc13783_viohi_val),

	MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),

	MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),

	MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0,	\

			    mc13783_violo_val),

	MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,	\
@@ -255,7 +255,7 @@ static struct mc13783_regulator mc13783_regulators[] = { 
			    mc13783_vesim_val),

	MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,	\

			    mc13783_vcam_val),

	MC13783_FIXED_DEFINE(REGU, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),

	MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),

	MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1,	\

			    mc13783_vvib_val),

	MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1,	\
@@ -266,12 +266,12 @@ static struct mc13783_regulator mc13783_regulators[] = { 
			    mc13783_vmmc_val),

	MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1,	\

			    mc13783_vmmc_val),

	MC13783_GPO_DEFINE(REGU, GPO1, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REGU, GPO2, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REGU, GPO3, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REGU, GPO4, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REGU, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),

	MC13783_GPO_DEFINE(REGU, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),

	MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),

	MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),

	MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),

};



struct mc13783_regulator_priv {
@@ -508,8 +508,8 @@ static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev) 
	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);



	/* Power Gate enable value is 0 */

	if (id == MC13783_REGU_PWGT1SPI ||

	    id == MC13783_REGU_PWGT2SPI)

	if (id == MC13783_REG_PWGT1SPI ||

	    id == MC13783_REG_PWGT2SPI)

		en_val = 0;



	mc13783_lock(priv->mc13783);
@@ -530,8 +530,8 @@ static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev) 
	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);



	/* Power Gate disable value is 1 */

	if (id == MC13783_REGU_PWGT1SPI ||

	    id == MC13783_REGU_PWGT2SPI)

	if (id == MC13783_REG_PWGT1SPI ||

	    id == MC13783_REG_PWGT2SPI)

		dis_val = mc13783_regulators[id].enable_bit;



	mc13783_lock(priv->mc13783);

include/linux/mfd/mc13783.h

+34 −33
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Yong Shen <yong.shen@linaro.org>

 * Copyright 2009-2010 Pengutronix

 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>

 *
@@ -122,39 +123,39 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, 
		unsigned int channel, unsigned int *sample);





#define	MC13783_SW_SW1A		0

#define	MC13783_SW_SW1B		1

#define	MC13783_SW_SW2A		2

#define	MC13783_SW_SW2B		3

#define	MC13783_SW_SW3		4

#define	MC13783_SW_PLL		5

#define	MC13783_REGU_VAUDIO	6

#define	MC13783_REGU_VIOHI	7

#define	MC13783_REGU_VIOLO	8

#define	MC13783_REGU_VDIG	9

#define	MC13783_REGU_VGEN	10

#define	MC13783_REGU_VRFDIG	11

#define	MC13783_REGU_VRFREF	12

#define	MC13783_REGU_VRFCP	13

#define	MC13783_REGU_VSIM	14

#define	MC13783_REGU_VESIM	15

#define	MC13783_REGU_VCAM	16

#define	MC13783_REGU_VRFBG	17

#define	MC13783_REGU_VVIB	18

#define	MC13783_REGU_VRF1	19

#define	MC13783_REGU_VRF2	20

#define	MC13783_REGU_VMMC1	21

#define	MC13783_REGU_VMMC2	22

#define	MC13783_REGU_GPO1	23

#define	MC13783_REGU_GPO2	24

#define	MC13783_REGU_GPO3	25

#define	MC13783_REGU_GPO4	26

#define	MC13783_REGU_V1		27

#define	MC13783_REGU_V2		28

#define	MC13783_REGU_V3		29

#define	MC13783_REGU_V4		30

#define	MC13783_REGU_PWGT1SPI	31

#define	MC13783_REGU_PWGT2SPI	32

#define	MC13783_REG_SW1A		0

#define	MC13783_REG_SW1B		1

#define	MC13783_REG_SW2A		2

#define	MC13783_REG_SW2B		3

#define	MC13783_REG_SW3		4

#define	MC13783_REG_PLL		5

#define	MC13783_REG_VAUDIO	6

#define	MC13783_REG_VIOHI	7

#define	MC13783_REG_VIOLO	8

#define	MC13783_REG_VDIG	9

#define	MC13783_REG_VGEN	10

#define	MC13783_REG_VRFDIG	11

#define	MC13783_REG_VRFREF	12

#define	MC13783_REG_VRFCP	13

#define	MC13783_REG_VSIM	14

#define	MC13783_REG_VESIM	15

#define	MC13783_REG_VCAM	16

#define	MC13783_REG_VRFBG	17

#define	MC13783_REG_VVIB	18

#define	MC13783_REG_VRF1	19

#define	MC13783_REG_VRF2	20

#define	MC13783_REG_VMMC1	21

#define	MC13783_REG_VMMC2	22

#define	MC13783_REG_GPO1	23

#define	MC13783_REG_GPO2	24

#define	MC13783_REG_GPO3	25

#define	MC13783_REG_GPO4	26

#define	MC13783_REG_V1		27

#define	MC13783_REG_V2		28

#define	MC13783_REG_V3		29

#define	MC13783_REG_V4		30

#define	MC13783_REG_PWGT1SPI	31

#define	MC13783_REG_PWGT2SPI	32



#define MC13783_IRQ_ADCDONE	MC13XXX_IRQ_ADCDONE

#define MC13783_IRQ_ADCBISDONE	MC13XXX_IRQ_ADCBISDONE