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Commit 57b32227 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville
Browse files

ath9k_hw: Update ath9k_hw_set_dma for AR9300

parent c14a85da
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+15 −3
Original line number Original line Diff line number Diff line
@@ -836,13 +836,16 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)


static inline void ath9k_hw_set_dma(struct ath_hw *ah)
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
{
{
	struct ath_common *common = ath9k_hw_common(ah);
	u32 regval;
	u32 regval;


	/*
	/*
	 * set AHB_MODE not to do cacheline prefetches
	 * set AHB_MODE not to do cacheline prefetches
	*/
	*/
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		regval = REG_READ(ah, AR_AHB_MODE);
		regval = REG_READ(ah, AR_AHB_MODE);
		REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
		REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
	}


	/*
	/*
	 * let mac dma reads be in 128 byte chunks
	 * let mac dma reads be in 128 byte chunks
@@ -855,6 +858,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
	 * The initial value depends on whether aggregation is enabled, and is
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 * adjusted whenever underruns are detected.
	 */
	 */
	if (!AR_SREV_9300_20_OR_LATER(ah))
		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);


	/*
	/*
@@ -868,6 +872,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
	 */
	 */
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);


	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);

		ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
			ah->caps.rx_status_len);
	}

	/*
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 * wrap around issues.
+6 −0
Original line number Original line Diff line number Diff line
@@ -39,6 +39,12 @@
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH         0x00060000
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH         0x00060000
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S       17
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S       17


#define AR_RXBP_THRESH       0x0018
#define AR_RXBP_THRESH_HP    0x0000000f
#define AR_RXBP_THRESH_HP_S  0
#define AR_RXBP_THRESH_LP    0x00003f00
#define AR_RXBP_THRESH_LP_S  8

#define AR_MIRT              0x0020
#define AR_MIRT              0x0020
#define AR_MIRT_VAL          0x0000ffff
#define AR_MIRT_VAL          0x0000ffff
#define AR_MIRT_VAL_S        16
#define AR_MIRT_VAL_S        16