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Commit 57a2b485 authored by Naveen Krishna Ch's avatar Naveen Krishna Ch Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynos7: add clocks for I2C block 



Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: default avatarNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 532abc3a

drivers/clk/samsung/clk-exynos7.c

+24 −0
Original line number Diff line number Diff line
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 
};



static struct samsung_gate_clock peric0_gate_clks[] __initdata = {

	GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 8, 0, 0),

	GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 9, 0, 0),

	GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 10, 0, 0),

	GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 11, 0, 0),

	GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 12, 0, 0),

	GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 13, 0, 0),

	GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 14, 0, 0),

	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 
};



static struct samsung_gate_clock peric1_gate_clks[] __initdata = {

	GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 4, 0, 0),

	GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 5, 0, 0),

	GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 6, 0, 0),

	GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 7, 0, 0),

	GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 8, 0, 0),

	GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",

		ENABLE_PCLK_PERIC1, 9, 0, 0),

	GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",

include/dt-bindings/clock/exynos7-clk.h

+14 −2
Original line number Diff line number Diff line
@@ -30,7 +30,14 @@ 
/* PERIC0 */

#define PCLK_UART0			1

#define SCLK_UART0			2

#define PERIC0_NR_CLK			3

#define PCLK_HSI2C0			3

#define PCLK_HSI2C1			4

#define PCLK_HSI2C4			5

#define PCLK_HSI2C5			6

#define PCLK_HSI2C9			7

#define PCLK_HSI2C10			8

#define PCLK_HSI2C11			9

#define PERIC0_NR_CLK			10



/* PERIC1 */

#define PCLK_UART1			1
@@ -39,7 +46,12 @@ 
#define SCLK_UART1			4

#define SCLK_UART2			5

#define SCLK_UART3			6

#define PERIC1_NR_CLK			7

#define PCLK_HSI2C2			7

#define PCLK_HSI2C3			8

#define PCLK_HSI2C6			9

#define PCLK_HSI2C7			10

#define PCLK_HSI2C8			11

#define PERIC1_NR_CLK			12



/* PERIS */

#define PCLK_CHIPID			1